ElEctric_EyE wrote:
After figuring some things out on paper, the only operation that would have to be done is to shift the cpu address to the right 6x, then truncate [31:21], to form a proper address for the videoRAM...
My brain must have been in software mode, because in the Verilog all I needed to do is a simple reassignment:
Code:
always @* begin //optimize the videoRAM address for plotting (X,Y) in the (LSB,MSB) for indirect indexed
cpuABopt [20:19] <= 0; //bank bits
cpuABopt [18:10] <= cpuAB [24:16]; //Y[8:0]
cpuABopt [9:0] <= cpuAB [9:0]; //X[9:0]
end
I've changed from a single linear pixel counter to a dual X, Y counter. I will have to change my character plotting software now for this new setup, but first I'll write a clear screen routine.
Then I can take advantage of the dual FPGA PROM and do a quick speed comparison. Linear addressing clear screen in 1 and optimized clearing in the other. They will be cycling through the 4-bit color look up table. Speed is back down to 50MHz. The addition of the X,Y counters put the design over the edge. It's ok though, towards the end of the project I can increase VSYNC and HSYNC frequency to boost the pixelclock then hopefully that will put the CPU closer to 80MHz.