Arlet wrote:
...Anyway, I kept the code, so if you ever need delayed I/O, let me know.
Thanks, I will have to flesh out the read timing to the RAM delayed by 2 cycles as you suggest first. That IOBDelay spec should bring things even tighter for even higher speeds than 100MHz I would think, i.e. if one was to consider running the SyncRAM at higher speeds in order to achieve higher resolutions.
In other matters, I am thinking of ways to
maximize plotting communication between the CPU and the HVSync modules. Old school 6502 software would have had to repetitively add the horizontal resolution to obtain the Y value and monitor the carry in order to increment the MSB, then add in the X value and again monitor the carry.
Today I was thinking of an idea to implement in Verilog that would be superior as far as execution speed is concerned when plotting individual pixels:
Integrate the X and Y pixel counters from the HVSync module and have them go direct into the 65Org16 and have a plot
opcode when X counter and Y counter both equaled the values present in 2 X/Y accumulators. Then the CPU would auto write the SyncRAM with a color value from a 3rd accumulator. The only issue being here is that the CPU is running at a multiple of the pixel clock frequency. This means that maybe other video timing signals maybe have to be brought into the CPU directly for the CPU to have it's own X and Y counters being run at a multiple.