Arlet wrote:
So, basically what they're saying is that the old address is valid for at least 10 ns after the edge, and the new address is valid no later than 40 ns after the edge.
I'm with you. That does seem to be what the diagram is saying.
Arlet wrote:
In that case, timing is really sloppy
If I'm right in guessing that these signals are registered on the falling phi2 clock, we're only talking about the propagation delays of the output drivers.
BigEd wrote:
I seem to remember the path goes through three transparent latches
I, too, wanted to mention transparent latches. Correct me if I'm wrong, but instead of using edge-triggered flip-flops I thought 65xx series chips operate by using their internal buses as transparent latches, driven "Phase-1, Phase-2" fashion so as to move data from place to place without creating a race condition. IOW, the address lines are not the output of an edge-triggered register, but are just a reproduction of whatever activity appears on an internal bus. If there's "sloppy timing" on the internal bus then that'd be reproduced on the address lines. Am I over-simplifying?
This still leaves the question of why sloppy timing might occur on the internal bus. My first thought is that the timing might vary according to selection of different address sources -- the Stack Pointer, the PC etc. But by running the Test Suite you're invoking all the options, and the 'scope shows no variability in the address lines' transitions. And yet, the people who wrote the timing specifications obviously
were worried about variability. Is it plausible that their (apparently unjustified) concern pertains to selection of different sources on the internal bus?
cheers,
Jeff
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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