Thank-you, all. Arlet, your INC example demonstrates (among other things) how VDA de-asserts during the "modify" cycle of a read-modify-write instruction. It's good to be reminded that VDA doesn't pertain only to indexed addressing issues.
BDD wrote:
from what I was able to determine, the STA $00D100,X instruction being used to write to the channel command register was actually hitting $00D100 on cycle four, followed by the correct address ($00D100+$02 or $00D100+$0A) on the final (fifth) cycle. That constituted two consecutive accesses spaced by only one Ø2 cycle, which violated the device's timing requirements
Interesting case. If the device gags on two consecutive accesses then that'd be a problem -- a problem that qualification with VDA will correct. Glad you got that sorted out; I can imagine how much "fun" you had.
One minor point: although the indexed address mode caused two accesses, they would not be to D100 then D102 for example. I think we've established that the issue is the CPU resolving whether or not the indexing addition produced a carry. If not, the two accesses will have identical addresses; if so, the two accesses will have addresses that are $100 apart.
Garth, I agree that only rare sets of conditions allow the carry-less access to result in a destructive read of an I/O device (different, of course, and more common than the problem BDD faced). As you say, trouble can arise if there's a table in RAM or ROM "that starts
in the same page with the I/O." But there's another wonky circumstance to consider. Say I/O is in page 7 and a small RAM/ROM table is in the bottom of page 8. Some poor schmo is coding away in assembler and wants to index into the table, but they know the value they have in the index register is, say, $80 too large. So, rather than inserting code to subtract $80 from the index register, they just subtract $80 from the hard-coded base address stated in the assembly source. That puts the base address in page 7...
Arlet wrote:
[The WDC programmer's manual] leaves open the possibility that the invalid address cycles are considered 'bugs', and therefore have been corrected.
OK, looking at the excerpts you posted I agree it's possible to take that interpretation. But the NMOS bugs (plural) they refer to as being fixed could merely include stuff like the $6C problem with operand xxFF, the fact that reset and interrupts ought to clear the Decimal Flag, the problem of a simultaneous BRK and interrupt, the invalid flags following Decimal operations... it's quite a list.
The scenario I envision is that they had their hot new product, the '816. The '802 was just a down-rated variant designed to fill a temporary need. I doubt there was any financial incentive for them to give the '802 the same workarounds that allow the 'C02 to avoid invalid addresses.
cheers,
Jeff
ps- Oops... sorry, BDD - didn't see your post until after entering my own. How'd THAT happen -- I though I had notifications turned on???
pps- I'll check and see if I have any 6SL7s for you...
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But for those of us who don't have test gear and an '816 system handy, just refer to Table 5-7 of the '816 Data Sheet. There's a 7-page listing of what the '816 does on every cycle of every instruction. Far fom being mysterious, the invalid address states are, as Garth says, quite predictable.