See bin2hex.exe

Excellent. Thanks, that works!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I have boiled the design down to CPU/ALU/RAMs/ROM & address decoding. A simple design so I can see if the cpu is running code in the simulator before adding in the video portion.

I'm thinking I might have a problem though, as I do not have a line physically coming out of the FPGA meant for a cpu reset, which is active high. I had been tying it low internally in my recent experiments. But I noticed that synthesis was negating chunks out of the cpu. So, I brought the reset line out of the top_level module and everything seems to synthesize much better and it takes longer.

Hmm, it must have a reset pulse to start running the program at the reset vector. Been away too long! Hopefully I can set something up, maybe hardwire the FPGA 'DONE' wire for a reset.

EDIT: Bah! I'm going to have to assemble the .h version with the 4 programmable pushbuttons on the backside. Won't be able to make further progress till next week. But I will post my code before then if I can get the sim working. I am using ISE14.1 currently.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Attached is the project file I've made so far. It is pure Verilog and I need some help.
I am having a hard time figuring out why ISE14.1 is giving me a warning:

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

On line 98 it says:

I'm guessing you didn't intend to use this clock output. There are 6 clock outputs, and you are only using clkout0, which is fine. This warning can be ignored.

That's what was confusing me, I see that part on line 113.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

More work is needed on this project file. I saw the error regarding the PLL frequency not being above 400MHz. I actually meant to have an internal 70MHz clock, not 35MHz. Also, I must include some sort of constraints file, even for a single basic input clock...

ISim is not working correctly using ISE14.1, seems to be stuck in a loop. I will report back.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

It is stuck in an infinite loop, but I fail to see where this is present in my code.

ISim says "Simulator is doing circuit initialization process.". Internet research on this confirmed my suspicion.

I've tried several different changes to the code with no luck. Any hints?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

When this happens to me, and it's not obvious what I've done to break the code, I attempt to discover the issue by using the synthesizer.

I suspect that it's a combinatorial logic loop that you've inadvertently constructed in your RTL. The ISim simulator doesn't generally flag them, but the synthesizer does issue warnings regarding combinatorial logic loops.

PS: another thing it might be is a loop in the test bench that does not have any edge events or time delays (#x). In other words, it's a test for event with no time dependencies, so it loops infinitely because time has essentially stopped in the simulator.

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Michael A.

The RTL schematic looks good...

I've done this project before in schematic entry and it worked, but now thinking back I had addressable ports hooked to a graphic LCD. In this project though, I do have the clock, cpuWE, cpuDatabusOut, and cpuAddressOut as outputs on the top_level, but now I don't think that this is enough even though the program in the ROM is doing a great many things to different memory locations. I think I may need at least a output port on the top_level. What do you think?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Your suggestion doesn't strike me as necessary for ISim to complete initialization.

It still feels to me that somehow you've got a loop which doesn't terminate/stabilize within a reasonable number of simulation cycles.

I tried to open your *.rar archive you posted earlier, but no luck. I must not have the correct archiver on my Windows laptop. Can you send me a link to a GitHub repo for your Verilog RTL and test bench source, or just send me the source by PM?

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Michael A.

Thanks, I sent a .zip. If that doesn't work, I'll just send the raw verilog files.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Michael, you have found a few errors in the code, which I'm grateful for you spending your time checking it out...

What version of ISE are you using?
And, Do you see the same "Simulator is doing circuit initialization process." message, where ISim is stuck?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I tend to use ISE 10.1i SP3. I have installed and uninstalled 12.4 and 13.4. I will soon receive the DVDs for 14.x.

Yes, I get the same message from ISim that you've been seeing. Nothing that I've found so far appears to be the cause of the simulation issue you've been experiencing.

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Michael A.

In your PM, you were focusing on the cpu.v, which made me think back to the last modifications I made based on some more recent updates Arlet had made to his cpu.v & ALU.v. I must have made an error. Also I should have tested the .b core after I made the mod's. I put in an older version of the .b core and the loop problem disappeared. Sorry about this!

This is not related to the loop problem but how the blockRAM's were configured. Earlier I had:which was synthesizing as a write-first style RAM, which was incorrect. I needed a no-change style RAM which the following code synthesizes correctly. Hopefully I will have this running tomorrow.
I am watching the console now very closely during synthesis!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502