Are there any people in cyberspace that have designed or built their own renditions of the 6502 processor ?

How faithfully does it represent the 6502 ? Have you added any custom instructions ? Have you changed it from 8 to 16, 32 or 64 bits ?


I'm currently working on my 5th! rendition. The first one was a Verilog implementation of original 6502 with no added features and it seems to work fine. The next three I've gotten partly finished then scrapped because I didn't like the look of the results. I just can't seem to do the 6502 justice.

I'm thinking of taking a different approach with this version. Originally I wanted a 32-bit version capable of also executing original 6502 code. But now I'm thinking of trying to capture the flavour of the original in a modernistic 32-bit form.

Rob

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I had sent an instruction suggestion to WDC the other day, and got an e-mail back from Bill Mensch himself. I was surprised at that.

Anyway, I recommended adding two instructions: ADX and ADY -- add a signed value to either X or Y. It would have the same addressing modes as CPX and CPY. Because the value added is sign-extended, there would be no immediate need for a SBX/SBY (subtract from X/Y) instruction. Also, ADX/ADY would behave as if the carry flag were pre-cleared. Thus, doing a 16-bit or 32-bit addition with these instructions would become about as efficient as doing an 8-bit or 16-bit addition with the existing processors.



While this is true, I wouldn't rank this as terribly high priority.

I would definitely consider, however, adding a rational math coprocessor to the chip. Why rational and not floating point? Because it works with integers and basically consists of an integer multiplier/divider, which takes a whole lot less transistors than a floating point processor. The only really specialized piece of hardware in it would be the rational reducer, which would reduce a fraction to its lowest form.

In addition, rationals can express certain mathematical quantities more precisely than floating point in the same memory space (e.g., 355/113 for Pi, for example).

Note that the dynamic range of the RPU (for lack of better term) wouldn't appear to be as great as an FPU at first, but there are three ways to mitigate this in software:

1. Use the RPU with an explicitly 65xx-managed exponent. This gives a hybrid approach that gives the advantages of both, at a slight expense in speed.

2. Take advantage of units. That is, why multiply a number like 25175000 by .0000009 when you know that the relative exponents of the two will cancel, and you need only multiply 25175 by 9 and scale the result to get the same value?

And finally,

3. Make the RPU scalable so it can handle multiple precision integers in both the numerators and denominators of each rational (e.g., give it a carry/borrow bit, and maybe a few other flags, to let it handle integers larger than it's natural word size). Even if this is done at the cost of speed, it'll still be much faster than the 65xx's own execution speed for this type of math.

This isn't as crazy as it sounds. When I was working for Hifn, I worked quite regularly with a "Bignum" coprocessor ironically called the 6500. The 6500 had 16 registers, each was 1024 bits in size. Yes, 1024 bits. It could do addition (with or without carry), subtraction (with or without borrow), multiplication, division, exponentiation, logical shifting, or any of the above in modulo arithmetic. While it wasn't used for rational math, lord knows it could easily have done so (we actually used it to support real-time cryptography and very high confidence random number generation). It could complete most operations in linear time, depending on where the most significant bit of the operand was located (internally, it had a 32-bit ALU). And it was fast -- faster than a Pentium at working with such large quanitites. Although, a Pentium IV did beat it ... finally.

I'm not sure if Hifn is still making these chips in discrete components; I'm pretty sure they are, but they're probably sunsetting them, as its core has been integrated into other, vastly more sophisticated network processor chips. Math coprocessors have never been Hifn's primary market anyway.

Anyone working on an existing 65816-based design that has a very high need for fast math with high precision, the Hifn 6500 is a very viable option for an external rational math coprocessor.

I had a look at that cpu that turned up on 6502 yahoo group.

I especially liked the "high-speed aluminum" arithmetic.

I guess google didn't didn't translate it with 100% accuracy.

Now that's the understatement of the century. And forget about translating anything inside tables -- those were still every bit as German as it could get.

That being said, I checked out Ruud's site, and saw absolutely NO mention of the 65GZ032 of any kind. If someone can provide a more detailed link, that'd be great. Otherwise, I have to assume the project has been killed off.

Hi Everyone,

Deffinitetly add "Swap nibbles".

The PIC and Z8 have it but the 6805/6811 don't.
8085, X86, Z80 and 68K also don't.
Motorola came to their senses with the 6808 and
finally added a swap nibbles command.


Bye,

Paul

This can be implemented fairly easily with a 256-byte look up table, but I still agree a swap nybbles instruction would be nice. It'd allow for some really fast shifts by 4 bits.

Perhaps something to consider are the following commands:



This would allow shifting of a hardcoded, though arbitrary, shift count in O(n log n) time instead of O(n) time.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The 65020 processor is a definite possibility for a viable 32-bit architecture. When I home-built my 4-bit processor (which didn't do anything useful, I might add, but it was fun all the same!) many eons ago, I upgraded the architecture to 8-bits by doing basically the same thing. While the 8-bit CPU read in only 8-bit instructions, only the low 4-bits counted (they were the same instructions as the 4-bit CPU), and the top 4 bits were ignored. Now I could have added a lot more instructions by using those top four bits, but if I kept them zero, they mapped to the original, 4-bit architecture's instructions.

This means that, if I were to write a loader for the 4-bit software on the 8-bit architecture, I'd do it the normal way, making sure to AND each byte with $0F. The software would run the same, with the same instruction timings.

I've always wondered why more people didn't extend their processor architectures that way. It seems like such an obvious solution to the problem of backward compatibility, and it keeps the hardware extremely simple. It's true that understanding memory layout becomes a bit of an issue, but with good documentation, only the whiners will complain.

Kudos to the architect of the 65020!

"In progress" is a bit of an overstatement. I've been promising myself I'll learn enough VHDL to do it for the past 10 years. One day...

Hello All,

Looking quickly on the discussion of HomeBuilt CPU's I wondered
if anyone on the list had investigated using a Coprocessor with
the 02 or 816. Are there any Coprocessors availible that can be used with the 65xx family ?

-Wally

I can't think of any, but I've often wondered how difficult it'd be to build a rational math coprocessor using simple register accesses (think TTA here). While the register interface wouldn't be hard, it's the guts that I've been wondering about.

Hi Everyone,

Here are some coprocessors that
target the PIC, but could probably
be used.

Enjoy!

http://www.al-williams.com/pak1.htm


Bye,

Paul