I just got home and tried it in the project and it doesn't fit.
Seems like it's best to have 2 comparators for linear memory addressing (beginning and end, code @ bottom) Chip Select signals vs. all the 'x's and the MUX's (maybe for a non-linear addressing, code @ below).
This is what I
had for the MUX's (slow):
Code:
module A_D ( input cpuWE,
input [31:0] cpuAB,
input [15:0] ZPP, //from CPU, zeropage pointer
input [15:0] SPP, //from CPU, stackpage pointer
output reg ram1CS = 0,
output reg ram1WE = 0, //pre-init to '0', not selected
output reg ram2CS = 0,
output reg ram2WE = 0, //pre-init to '0', not selected
output reg rom1CS = 0, //pre-init to '0', selected
output reg vramCS = 0,
output reg rndgCS = 0,
output reg cntrCS = 0
);
// address decoding for internal blockRAMs
always @* begin
ram1WE <= ( !ram1CS && cpuWE );
ram2WE <= ( !ram2CS && cpuWE );
end
always @*
casex(cpuAB [31:0])
32'b1111_1111_1111_1111_1111_xxxx_xxxx_xxxx:
rom1CS <= 0;
default: rom1CS <= 1;
endcase
always @*
casex(cpuAB [31:0])
{SPP,16'b1111_1100_xxxx_xxxx}:
ram2CS <= 0;
default: ram2CS <= 1;
endcase
always @*
casex(cpuAB [31:0])
{ZPP,16'b0000_00xx_xxxx_xxxx}:
ram1CS <= 0;
default: ram1CS <= 1;
endcase
always @*
casex(cpuAB [31:0])
32'b0000_0010_xxxx_xxxx_0000_0010_xxxx_xxxx:
vramCS <= 1;
default: vramCS <= 0;
endcase
always @*
casex(cpuAB [31:0])
32'b1100_0000_0000_0000_0000_0000_0000_000x:
cntrCS <= 1;
default: cntrCS <= 0;
endcase
always @*
casex(cpuAB [31:0])
32'b1010_0000_0000_0000_0000_0000_0000_0000:
rndgCS <= 1;
default: rndgCS <= 0;
endcase
endmodule
This is what I have reverted back too:
Code:
module A_D ( input cpuWE,
input [31:0] cpuAB,
input [15:0] ZPP, //from CPU, zeropage pointer
input [15:0] SPP, //from CPU, stackpage pointer
output reg ram1CS = 0,
output reg ram1WE = 0, //pre-init to '0', not selected
output reg ram2CS = 0,
output reg ram2WE = 0, //pre-init to '0', not selected
output reg rom1CS = 0, //pre-init to '0', not selected
output reg vramCS = 0,
output reg rndgCS = 0,
output reg cntrCS = 0
);
// address decoding for internal blockRAMs
always @* begin
ram1WE <= ( !ram1CS && cpuWE );
ram2WE <= ( !ram2CS && cpuWE );
if ( (cpuAB >= {ZPP,16'h0000}) && cpuAB <= ({ZPP,16'h03ff}) ) //1Kx16 zeropage RAM address decode w/ZPP reg as the MSB pointer
ram1CS <= 0;
else ram1CS <= 1;
if ( (cpuAB >= {SPP,16'hfc00}) && cpuAB <= ({SPP,16'hffff}) ) //1Kx16 stackpage RAM address decode w/SPP reg as the MSB pointer
ram2CS <= 0;
else ram2CS <= 1;
if ( (cpuAB >= 32'hffff_f000) && (cpuAB <= 32'hffff_ffff) ) //4Kx16 'initialized RAM' ROM address decode
rom1CS <= 0;
else rom1CS <= 1;
if (cpuAB >= 32'h0000_0000 && cpuAB <= 32'h0280_01e0) //video space
vramCS <= 1;
else vramCS <= 0;
if (cpuAB == 32'ha000_0000) //random number generator, read only
rndgCS <= 1;
else rndgCS <= 0;
if (cpuAB >= 32'hc000_0000 && cpuAB <= 32'hc0000_0001) //cycle counter
cntrCS <= 1;
else cntrCS <= 0;
end
endmodule
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