Hi, I'm new here but I've been lurking for a while.

I'm working on my own 6502 based SBC and I am not quite sure of the best way of handling the bus for some peripherals.

SRAM: Most people seem to gate Phase2 with the a decoded address line, to create a /CS, then either tie to /OE or leave /OE asserted. Is it valid to invert ph2 and send that to /OE instead? I would have thought using /OE for the ph2 might have been more efficient for some SRAMs, then it occurred to me the SRAM may get confused by invalid states of the address bus while ph2 is low? (As /OE likely only prevents asserting the data bus?)

ROM: Most EEPROMS have a /WE pin, and from datasheets I've read, it should be adequate to invert R/W and send it there. Is it a better idea to qualify a /ROMCS with R/W?

65C52: I'd like to have two serial ports and the 65C52 seems ideal. However I've noticed that unlike the 65C51 the '52 has no phase2 pin. Anyone have experience here? I'm guessing gating a /CS with ph2 should be adequate as I cannot see why the '52 shouldn't honor ph2. But if I don't need to, I'll save the gate.

Thanks!

You must have a way to make sure the RAM cannot be written when phase 2 is low. The address lines are not guaranteed to be valid and stable before the R/W goes low; so it is possible to write to unintended addresses if the WE\ or CS\ is not qualified by phase 2. (You don't have to qualify both, but at least do one of them. WE\ is the better one to do for higher speeds; but it may not matter since ROM is generally slower and more likely to be the speed bottleneck than RAM is.) Note that OE\ is not involved in this. This is covered in the address-decoding page of the 6502 primer. On the 6502, it is ok to let something put data out on the bus when phase 2 is low, but this is not true of the 65816 since it is putting the bank address out at that time, and there would be bus contention.

I have not used EEPROM myself, but note that it takes time to write. It is not as fast at writing to as RAM is. The WE\ polarity is the same as R/W\ though, so that would not need to be inverted. Low=write.

The 65c52 interested me too years ago, but I have never seen one. The 65c51 is being made today by WDC in 14MHz+. I've used the '51 a lot and never had any trouble with it, although I wish a couple of the controls had not been merged into one bit. Another option I've used is the more-capable 14-pin-DIP MAX3100 UART which is interfaced through SPI. I cover I/O ICs on the I/O ICs page of the primer, and in the circuit potpourri page.

_________________
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What's an additional VIA among friends, anyhow?

Thank you for the response to this. I'm guessing from this that anything that can be written to should have a /CS (Not /OE) gated with phase 2, unless they are 65-series with a phase 2 input. I'm using a DS1511Y clock, as in BDD's POCv1, and that has write-able registers and some SRAM too, so I expect the same rule applies.

The 65C52 seemed easy enough to find on Ebay, I got a new R65C52P4 for a reasonable price and had expected it to be more popular. If it turns out to not play nice I'll fall back to the 65C51.

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Hi BDD
are you saying that you use VDA and VPA as strobes to qualify the validity of address outputs on a nanosecond basis? I would have expected these signals only to obey the usual synchronous output behaviour, and be valid on a cycle basis.

as you say, one wants to qualify at least any write operation with something which limits the access to a period when the addresses and RnW line are both stable. It's surely conventional to do that with the phi2 clock: it comes a little later than it might, but it is late enough to do the job.

it has been said elsewhere that some old peripherals don't allow for that: they need inputs stable before rising phi2.

Cheers
Ed

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Hm, it's late so I hope my cluelessness isn't going to start arguments.


Using the 65C02 for now, but may switch up to the `816 for a subsequent SBC. It's on order.


I'm guessing that's desirable rather than mandatory, as I have seen I/O devices that only have a CS or E, and RWB. Directly attaching an HD44780 LCD to the bus is an example, where I wanted to preserve VIA pins. http://6502.org/mini-projects/optrexlcd/lcd6502.gif

I guess I was implying in my original post though, that for non-65* devices that don't have a Ø2 input, is it always mandatory to honor Ø2 for all devices that accept bus writes? Eg: a DS1511Y or HD44780, as well as SRAM.


So if I am reading it right: It is better to qualify RWB with Ø2, to avoid wild writes on devices that have no Ø2 input, and let address-decode generate CE. In general. The only issue there is that the device might try to assert the data bus while Ø2 is low, even though nothing cares what information is on it. I guess the 65C02 won't care about that enough (electrically) for it to be any concern?


That is why my old Datasheet for my R65C52P4 is a head-scratcher, it appears to have no Ø2 input yet has NC pins. I've searched high and low for a more recent datasheet to no avail. Yours and Garth's points regarding substituting a better UART are noted. It's just I have this part plugged into my breadboard right now. If I can get things running (and TBH I am not yet at the point of cutting code) I'll report any findings on the device for completeness sake. I have a 65C51 on order anyway, but promise I won't sully an `816 with it.


Thanks for your responses, I am still in the research phase and my iron is still cold. I had already taken your recommendations for 74AC parts while studying your POC pages. Starting out, my plan was to begin at 1MHz with a 65C02, 65C22, 65C52(51), 27C512, 61512, DS1511Y, and a HD44780 and improve from there while keeping it as simple as possible.

(Yes, I find BDD often mixes in mandatory with advisory. Sometimes I ask for clarification.)

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

I Agree, I have a 26C92 (it's a 40 pin dip), I'm using one of the uarts as a serial port for computer 232 connection and the other uart as a TTL serial port to a voice synthesizer. Plus there are some input and output ports, I used a few of those to generate an i2c port. There are also some counters for generating short time delays.

I just looked at the timings on the '52, something I had never done before since I had never seen a '52. The falling edge of the CS\ latches the register-select and R/W\ signals; so those have to be in place by the time the CS\ edge falls. (The data sheet is at http://6502.org/documents/datasheets/ro ... _dacia.pdf, but I looked in my Rockwell data book.)

For the 65c22 and 65c51, the R/W\ line definitely has to be valid and stable well before phase 2 rises. For other I/O ICs that don't have a phase-2 input, you won't want them to be both selected and write-enabled before phase 2 rises. More precisely, the problem is not that the data won't be correct yet. It might still not be correct yet when phase 2 rises, but it will be correct in time to meet the device's set-up time before phase 2 falls. So that's not it. The problem comes in when the user uses an IC without a phase-2 input and he ignores the fact that the address lines and R/W\ take on their new state at the same time instead of address lines being valid and stable before R/W\ falls.

I said I've never had problems with the '51, but I should qualify that. I've never used the 6551 (NMOS) which definitely has a couple of major problems that were fixed in the 65c51 (CMOS) version.

I have 32KB of ROM on the workbench computer because my very full-featured Forth does not fit in 8KB and I didn't want to load it every time; so I can see a reason for more ROM. I have 16KB of RAM and it has always been plenty for programs, just not data when I would like to have many megabytes of arrays, something that won't be satisfied with a full 65c02 memory map anyway.

BDD has apparently found some ICs that cause problems if both WE\ and OE\ are asseted at the same time. I have not seen any. I'm not doubting that they exist, but see if the data sheet will let you get off the easy way. It seems like most will disable their outputs when you enable writing.

On the LCD: I've put one directly on the bus before, but it was not nearly fast enough to put it on the bus of my workbench computer at 5MHz. Look at its timing spec.s, and if it's too slow for your 65c02 bus, you will probably want to go through a 65c22. I show one way of doing this at http://wilsonminesco.com/6502primer/potpourri.html#LCD

I show a very basic 65c02 computer's full schematic at http://wilsonminesco.com/6502primer/pot ... ml#BAS_CPU . The accompanying notes tell how to add more I/O, like more 65c22's and a '51 or two. The glue logic already shown there (a single 74xx132!) is adequate for the whole job.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?