After a hard working weekend adapting the code from AVR Assembler to gcc this is the final result: A beautiful sync between clock and chipsel for the 6522.

ATMega @16MHz, 1MHz OC0B with Timer 0, CS=1 active, while loop calls sync_wrt() repeatedly. If you watch closely you even can see the fingerprint of the code, 7+1 clock cycle for the NOPs causing the voltage drop respectively.

Nice.

Thank you, Klaus.