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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I thought I've seen dense boards. This is incredible. Talk about 3-D technology!

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Gives me an idea.. You could solder a stack of chips 'surface-mount' style to two boards, one on either side, if your pack of chips is aligned neatly. This would require a template to hold the stack together, and very little effort - one shot in the oven. You can't visually inspect the solder joints, but it's no worse than BGA.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

UPDATE... I wasn't happy with the power distribution and decided to use a larger FPGA. 20 2KB BRAMs allow for a lot of ROM, and there is a lot of logic for custom video chips or whatever.

XC3S700AN FPGA
Bottom edge: 2x wing-compatible connectors outputting 12 bits each
Top edge: 22x2 card-edge .1" 41 I/O pins + 5V, 3.3V and GND.
3 additional outputs and 2 LEDs
512KB or 128KB RAM
Socket for a captive WDC 6502 or 16 chip.
JTAG connection

The entire board is intended to plug into a 'motherboard' containing controller IO and video, specialized for a particular retro-machine... I have a preliminary design for an Apple2 base with an SD card.

The board can be also used as a standalone devboard with a couple of wings, or breadboarded (by populating the top row of the wings + 2 power pins with male pins).

I've been building a PID hotplate for messing around with BGAs at home... Easier for rework than the oven.

If everything works as planned I should have a few prototypes in a couple of weeks. For my friends on this board I can make a few extras at cost (should be under $75).

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Very nice indeed!
Edit: (But I entirely failed to make or anticipate Arlet's point below!)

Where's the socket for the 6502 ?

It' on the back along with the power regulators:

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Ah, we don't need no stinking jumpers! Every pin of the socket (except for the 3 power pins) goes to the FPGA. Same with the SRAM. The chips are entirely sandboxed. A very simple piece of Verilog will connect the clock, the address bus of the CPU to the SRAM, and a slightly more complicated one will deal with the data bus, accounting for direction. High address lines will also select FPGA BRAM as a ROM. Add a counter and some I/O and you have a KIM-1.

The choice of '02 or '816 is up to you and the FPGA configuration. Incidentally, the XC3S700AN should be big enough for one of the mutant CPU cores.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Or, if you wanted to be truly dynamic, you can feed the CPU some detection code when it first resets. This code would figure out if it was running on a 65C02 or 65C816, and write an I/O register so that the FPGA could switch to the appropriate environment.

This is probably overkill though. Just providing a different bit file would be easy enough.

Enso:

Sorry to jump into this now, but the Spartan-3AN FPGA is not 5V tolerant in any way. Its maximum absolute ratings is +4.6V. I ask because I don't see any level translators between the FPGA and the processor. The WDC W65C02S is capable of being operated on +3.3V, but I can't make out whether you've connected it to the +3.3V bus or the +5V you have routed around the board.

Further, I see where you mentioned changing to the XC3S700AN part. That is a very nice part. I designed into some products used in industrial printers, and it is very easy to work with. However, it's going to require significantly higher static current than the XC3S200AN you first started with. As I see it, you are not using a +3.3V or GND plane in the design. At 14 MHz operation, with the short connections to the processor and memory, it may not cause an issue. Regardless of the power distribution approach, I am concerned that without the power planes your two little linear regulators will not handle the power dissipation required since they are not heatsinked into the power planes.

I did a quick calculation for the static and dynamic power required by the 65C02, and at 14 MHz I calculate a static power load of 14 mA plus a dynamic load requirement of 38.4 mA ((16+8) * 1.6 mA). This load coupled with the higher static power requirements of the FPGA, and the high-speed SRAM may be more than enough to cause some thermal limiting issues for your power supply.

For the +3.3V supply, I might look to using a 78xx-series switching regulator instead of a linear. That series of switching regulators is very small, and as the part number implies, is marketed as a drop-in replacement for LM78xx-series linear regulators widely used in the 80s and 90s.

A few more comments, if I may. I recommend connecting the oscillator to one of the global clock pins on the FPGA in banks 0 or 2. Further, connect it to a clock pin intended for the 'P' (plus) of a differential clock input. There are some limitations as to how the clock buffers may be used inside of the part if the clock input is supplied though the 'M' (minus) pin. I further recommend the same for Phi2O and Phi1O. I might use bank 0 or 2 for the oscillator, and the opposite bank for the clock outputs of the 65C02. Finally, if you envision an external device writing to your board through the FPGA with a write strobe (asynchronous bus), I recommend that signal be attached to a global clock pin in banks 0/2 as well. It will not be nice if an external write strobe has to be routed from a general I/O pin to a clock buffer far removed from the input itself; very little can be done to reduce the resulting clock skew.

BTW, good compromise to rotate the FPGA 45 degrees from the PLCC and SOP packages.

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Michael A.

It looks like there's enough room around the regulators to include a copper pour as a heat sink. I assume the board is intended to be run from 5V, so the regulator only has to drop 1.7V, which limits the power dissipation.

Thanks for the input, I was hoping for comments. Sorry about the low-res, I will put up a bigger picture/design files (it's all opensource anyhow - feel free to use it any way you like).

-WDC socket is wired at 3.3V. Specs seemed to imply maximum speed of 8MHz as I recall (I will empirically test it pretty soon). I can't see a simple way to improve it without a lot of real estate.

-ST's LD1117DTs are rated at 800mA and I was assuming that's more than enough power. I will look into switchers... Heat dissipation is a concern; I will create larger pads at least. I don't think it's necessary to heatsink based on other designs I've seen. I no longer plan to sandwich the board but keep it in an edge socket.

-Crystal oscillator is connected to Bank 3 pin L3, labeled L2IN_3 LHCLK1. Is there something wrong with bank 3? I will look into it, and the +/- connections.

-Power planes... Yes, this is not an ideal situation, I am well aware. This design is 2-layers, so it's a compromise. Maximum speed is pretty low (well under 100MHz).

The backside shows vertical power distribution lines, and they are almost entirely covered with decoupling caps. The power grid between the regulators, SRAM, FPGA and WDC socket is very short. Is it worth creating partial planes by flooding rectangles? I am not sure.

A bunch of pins on the edge connector wind up with clock-capable pins from bank 3 and 0. I didn't think too much about it, just worked out.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut