I try to explain my simulation of whole /NMI pin logic.

Overview:


So I simulate output as follow:


(b is temporary value)

I drawn NAND/NOR counterpart of trigger on picture. So I think we need those "~".

As output I'm getting following data:


Where :
L - latch value before iteration
N - NMI pin level
Ф - PHI2
L* - latch value after iteration
O - output line

And it even worse, if you try to simulate /IRQ. It has additional PHI1 transfer gate + latch as output. In that case I'm getting only '1's on out.

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6502 addict

It's not a nor of a NAND: it's a nor of an and.

Indeed, this is NOR of ANDs, I just checked truth table, thanks ))) Now everything works good )

Transition states of /NMI output line:


Transition stated of /IRQ and RES lines (both have additional output static latch):


Simulation can be found here:
http://code.google.com/p/breaks/source/ ... SRC/MISC.c

(I added some convenient macros like NAND / NOR, to increase source code readability)

Also I started my 6502 debugger:

It may look more complicated, than other 6502 debuggers you've seen before

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6502 addict

And another thing I want to show you:

http://ogamespec.com/6502/PLA.htm

This is tracing of PLA lines for every opcode on each cycle.

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6502 addict

Great stuff!
Have you tried to run your Breaks6502.exe on Linux using WINE? I'm willing to try it if you make the exe available (maybe in a zip file)
Cheers
Ed

It should run under WINE without any trouble. I'm using plain winapi.

Here:
http://code.google.com/p/breaks/source/ ... runk/Build

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6502 addict

Thanks - it does open the front panel and another window! Some but not all checkboxes work, and the Step button causes the clocks to toggle and produces some output on the console. (I don't see anything in the second window)

This is a good sign, I think, for Linux users.
Cheers
Ed

Its not ready yet I'm going to start simulate random logic soon. Most interesting part of my research )

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6502 addict

Understood - look forward to more updates!

Fixed some errors in PCL circuit and completed Program Counter increment logic.

I do not know why PCHS/PCLS registers are get inverted after every PC increment.

For example when PCHS/PCLS=0x1234 incremented, it become 0xEDCA (inverted 0x1235). So if you try to increment it again, without altering PCHS/PCLS it become again 0x1234 (inverted 0xEDCB)

I guess PCHS/PCLS is additionally inverted somewhere through ADH/ADL bus for example (since PC is connected to ADx bus via some drivers)

PC get incremented when IPC driver become low.

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6502 addict

Completed Predecode logic simulation.

Predecode has two outputs : /TWOCYCLE and /IMPLIED.

Predecode determine whenever instruction takes 2 cycles to execute or it has no operands (implied).

Two-cycles instructions are actually all implied (except push/pull) + ALU operations with immediate operand.

I attached screenshots with list of 2-cycle and implied 6502 instructions.

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6502 addict

Do you still have the inverting PC problem? I think it must be a bug - I'm pretty sure I've never seen it on visual6502.

I'm going to research reset sequence, to know more details on PC updating, so it must be fixed.

I cannot detect bug, by looking from inside of PC logic.

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6502 addict

In case you guys remember me, I started my own site for Breaks project:

http://breaknes.com/

And I'm gonna return to 6502 soon, I have some progress to show you )

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6502 addict

Very nice - I'm surprised that Icc isn't the best compiler for Intel.

How much 6502 simulation is working now? Can you run short instruction sequences?

Cheers
Ed