I'm sure that a cycle-accurate 6502 model using only one clock edge is perfectly possible, if indeed we don't already have one somewhere. (Arlet, yours is special because of the use of synchronous memory, I think.)
It's true that the NMOS 6502 is a two-phase design, and it's true that the Z80's approach is to use multiple cycles (T-states) for access. (The Z80 has an easier time of driving the strobes of a DRAM as a consequence.)
It's also true that designs using the 6502 commonly use phi2 as a kind of strobe, to have a mid-cycle demarcation. But as Arlet's figures show, even the CMOS version of the CPU doesn't have any external behaviour which relates to the rising edge of phi2. Only the falling edge.
And, it's also true that several designs using the 6502 make use of the fact that RAM access times are somewhat shorter than a half-cycle, to allow for two RAM accesses within one clock cycle, where the second RAM access is for video (or maybe other things?) This is clever, but it amounts to double-clocking the RAM, not as evidence that the 6502 is double-clocked.
As an interesting illustration of other approaches, see
the Oric:
(I was once in a death-march CPU project with a target of 30MHz, which was struggling to meet 10MHz, and was asked by a senior manager whether our 4-phase clocking would allow for a marketing position as a 40MHz part (or maybe one day as a 120MHz part.) Being the kind of engineer I am, I was very direct in saying that it wouldn't. Probably career-limiting, but that's me!)
What I mean by this (in the nicest possible way) is that it's a misuse of terminology to say it's two CPU clocks for a memory access. The NMOS 6502 is certainly a two-phase design, but any other implementation need not be, even an indistinguishable one.
Michael: thanks for your analysis. Note that the transistor count from the visual6502, which has I think made its way into Wikipedia, is only a count of pull-downs. So an inverter is only a single transistor, and an N-input gate is only N. The NMOS 6502 was found to use transparent latches extensively: they cost only two transistors. But the net effect (as you imply) of a pair of transparent latches clocked on opposite phases is an edge-triggered flip-flop. As I say above, we can model all the behaviour of a 6502 using edge-triggered flops. What you find is that the address bus cannot be driven directly from a flop, but must be driven via a mux. This, together with the need to get from the data bus capture flops across to the address bus pins, is the reason that the address bus becomes valid a bit later than you'd like.
Cheers
Ed