You're likely to get a reaction from that! All the action happens within one clock tick: these are asynchronous memories. The Address values settle fairly early in the cycle, and the data latch closes at the end of the cycle.
Cheers
Ed

Rather than arguing about whether to call this 1 or 2 cycles, let's just say the 6502 requires the memory to have an access time of less than half a cycle. The Z80 allows 1.5 cycles.

A bit less than a cycle, sure, but I don't see that it's half a cycle for the '02

Ok, not quite less than half a cycle, but close. The original 1MHz NMOS 6502 specified 500ns access time, or exactly half a cycle. The WDC 65C02 has 290 ns access time for 2 MHz clock (58% of a cycle), and 30 ns for a 14 MHz clock (42% of a cycle). All read cycles.

I knew it would cause a reaction. Now calm down friends. My point is that if you output and address and flop in the data in 'one cycle', I would really call it two. Consider a '1MHz' computer that is accessing memory every other '2MHz' cycle - let's say Apple 2. The other, unused '2MHz' cycle is used to generate the display, without slowing down the 6502. You can say 'the memory is running at 2MHz and the processor at 1MHz, but only during Phase2' or whatever. I would say that a more rational way to describe such a behaviour is to say that the processor is running at 2MHz, and that the memory is accessed every other cycle... Just because the manual calls it one cycle, it doesn't make it so for me.

Imagine designing a 6502 in an FPGA or an ASIC, timing-accurate. You can run a 2MHz clock, or you can use the negative edge as well as the positive edge. Or use an out-of-phase clock. Your marketing people will either say 'featuring an amazing 2MHz speed', or 'beats all other processors while still running at 1MHz'.

I say tomato, but you say tomato.

BTW, I do enjoy buying 2 bridges for the price of one.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

I'm watching to see where your 'bridges' go. Very interesting stuff. Welcome!
I have a few suspicions where you're from, but I'll keep them to myself.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

ElEctric_EyE, perhaps nothing escapes your hawk-like electric vision. Anyway, the 2-for-1 bridges I keep buying may or may not lead anywhere

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

enso, you modified your previous post. You previously mentioned a 6502 "core inside an FPGA". I was just wondering which "core"?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The post above was edited for a typo - after much editing the original post wound up saying " Consider the '1MHz' computer", changed to " Consider a '1MHz' computer".

If you are referring to my 6502 playground post - I am mostly using Arlet's core, although I've been messing around with a homemade BRAM-based core that should synthesize to about 100 slices and a BRAM, if I ever finish it.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

If you started with a 2MHz input and the processor itself divided it down to 1MHz, then I could accept that. 'Tis not how it verx though.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Well, I challenge anyone to come up with a way to implement a timing-accurate - to 500ns for a '1MHz' 6502 - model without either a 2MHz clock or using both transitions of the 1MHz clock. You have to do things on the posedge of a 1MHz clock. And no tricks like creating a delay - that's the same as having another clock in order to do two cycles in one. The implementation can be a theoretical one.

I am a purist. When you do things 500ns apart, I would really say you are running at 2MHz.

Not that any of this matters of course. Tomato.

And please do not take offense. We are all bound by our mutual love of the 6502...

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Oh, and if you have any illusions about pipelining, consider the case of a 3 cycle jump. (I mean a 6-cycle jump

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Eesh, now I am off on a crazy semantic hunt...

According to Wikipedia, "the two phase clock (supplying two synchronizations per cycle) can thereby control the whole machine-cycle directly". Two synchronizations per cycle? What exactly makes it a cycle if not the synchronization?

So we probably agree that at least some part of the CPU is running at half-clocks or so. Now we are in deep mud - how much of this somewhat asynchronous CPU is running at 2MHz? Just the memory addressing logic? Someone probably knows.

Here is another question. Let's say I run at 10 kilometers per hour, but every other second I freeze for 1 second. Am I running at 10 k/h or 5? Let's say a policeman with a radar clocks my instantaneous velocity at 10 (some of the time). Let's say I arrive 5 clicks away an hour later. Who is right?

I say I am running at 10, but need to stop every second to catch my breath. Many of you seem to think it's 5, but it's not really the same as running at a steady pace.

If you are not convinced, what if I run at 10 for 8 hours, then sleep for 8 hours. It would not be fair to say that I run at 5 kilometers per hour. I really do run 10...

I don't know.

I still think that a Z80 is a little more honest about requiring 2 cycles to address memory. The 6502 just hides one of the cycles with fancy footwork.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

The technology of the time did not allow the generation of fancy clock multipliers. I would venture to say that an examination of the Visual6502 project will show that there are no such clock generation circuits employed in the NMOS device. Furthermore, from the descriptions and circuit diagrams provided by those evaluating the actual chip implementation, I gather that latches and transfer gates are the predominant bi-stable elements and bus switching circuitry employed in the device itself.

If I remember correctly, the most staggering statistic I've gleaned from the Visual6502 project is that only about 3600 transistors were used in the implementation of the original microprocessor. This is a remarkably small number of transistors for such an elegant processor. At least two transistors are required to build a latch, and an edge-triggered FF requires at least a master and a slave latch plus an additional transitor or two for clock pulse steering and/or inverting to control the two latches.

Assuming that 6 transistors are used, then 3600 transistors can be used to construct 600 FFs. The various registers, A, X, Y, S, PCH. PCL, and P, require at least 6*(8*6+6) transistors, or about 324 transitors. Additional FFs such as Memory Address registers, and Data Input and Output registers, and other temporary working registers likely brings up the number of FFs to 6*8*6, or an additional 288 transistors, for a total number of 612 transistors used for D-style FFs. Various gates have to be constructed to pass the various registers around on one or two internal busses. Assuming 2 eight bit busses, and a total number of registers around 112, then an additional 224 transistors are used as bus drivers. At this point, 836 of 3600 transistors have been used for just registers and bus drivers. The remaining 2764 transistors would be required to implement the ALU, the sequencer, and any other random logic that may be required. The control ROM probably requires some for buffering, but none for the implementation.

The point is that a two phase clock, where one phase enables some latches, and the other phase enables other latches, will result in a more efficient implementation from the perspective of transistors. Timing and layout of the circuits are certainly more critical. Transfering data from one latch to another with latches is more difficult. A non-overlapping two phase clock, like that of the 6502, is essential to type of operation.

Many of the fastest computers of that time (CDC 6600 and CDC 7600) were built with latches using pulsed enables. One very interesting control approach used by DEC in the PDP 6 was a delay line where the taps essentially determined the control transfer points in a sequential circuit; a form of microprogramming (according to DEC). A pulse was entered into a delay line and at predetermined delays which matched the performance of the preceding logic circuits, a control pulse would be extracted and used to initiate the next operation of the sequential logic circuit. It's like using a series of '123 one-shots to march a computational function along to completion with the pulse from the last one-shot latching the result into the final register/latch.

As our ability to integrate transistors has improved, we've adopted more stable and easier to control design methodologies. In the process, we've lost a significant amount of technology. Latches are deprecated as design elements, even for those problems where they are clearly superior. For example, an 8031 microcomputer with its multiplexed address and data bus would require extremely fast ROM/RAM if instead of a '373 octal latch, the least significant byte of the address was demultiplexed using a '374 octal register. The additional address setup provided by the latch allows the use of substantially lower speed memory devices.

I tend to think of multi-phase systems like the 6502 in terms of latches and transfer gates. When this approach is used, the first half of the cycle is the setup phase, i.e. loading of the master latch in a FF, and the second half of the phase is storage phase, i.e. the transfer of the master latch to the slave latch in a FF. These two operations can not be counted as separate; they are both required and as such form a single cycle. As separate, independent operations, they are incomplete.

Using registers (FFs) is fine, and all of our FPGA/CPLD implementations have to use registers since the delays between latches are harder to control in an FPGA/CPLD. (It is virtually impossible to provide non-overlapping latch gating signals in a PLD for a large number of latches.) Invariably, our PLD-based 6502s use many more resources than Peddle and company used when they implemented the NMOS 6502. I attribute this primarily to fact that we tend to use registers and multiplexers rather than latches and pass transistors.

I am always amazed at the elegance of the implementation of the early microprocessors. I find it very instructive, from a hardware design perspective, to study these old architectures. Their implementations are certainly nothing that a recent graduate will ever have been taught, and that is definitely a problem.

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Michael A.

Oh, I don't mean to imply that there is a clock doubler inside the 6502. I am just saying that during every 'cycle', two distinct operations happen. By modern standards, these would be considered independent cycles. Or to put it another way, something happens DDR-style, on up and down transition of the clock, which is pretty much equivalent to clock doubling.

Add to that the memory running at double speed, and in my mind, we have a strange situation.

The 6502 is the most incredible piece of hardware I've witnessed in my life, and I don't wish to demean it in any way. If anything, I continue to be totally amazed as I learn more about it.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut