I've been toying with an idea for a while. Well, more than toying - I am actually prototyping this thing I am about to describe...

A WDC 65C02 has every pin (other than 3.3V and ground) connected to a Xilinx XC3S200AN or 700AN. A 128KB RAM is connected to the same FPGA. Also, a crystal. A bunch (64?) of pins from the FPGA are connected to expansion sockets (perhaps wing-style). The board is programmed with a 6-pin JTAG cable.

The 65C02 is completely sandboxed and controlled by the FPGA, presenting the following usage scenarios:
- A basic computer. BRAMS in the FPGA are mapped as a few K of ROM for monitor etc. Serial communication via 3.3V pins or a wing with RS232.
- A more sophisticated device with memory management in 8K chunks(or pretty much any size chunk)
- A clone of Apple, Commodore, whatever. The FPGA provides the missing circuitry; expansion boards provide SD storage, video output, keyboard etc.
- A 6502 core verification device. Run 65C02 in parallel with an FPGA core, sound alarms on state mismatches.
- A KimKlone-style 6502 augmentation. Since the FPGA oversees memory access, we can override any instruction, illegal or legal.

My goal is to keep the board simple and small. It should function as a self-contained SBC, and boot from the FPGA in the minimal configuration. For more advanced systems, the expansion boards can take care of what's necessary.

The idea was prompted by the address decoding discussions on this board. It seems that having programmable logic makes sense, and having a small FPGA makes it possible to build all kinds of peripherals very easily. The price difference between a handful of logic chips, a CPLD and a small FPGA is pretty small these days.

If there is enough interest, I could make few extra boards. I have a bunch of 200ANs and 700ANs itching to become something...

Feedback appreciated.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Nice idea (distantly related to the propeddle) - how many pins on your FPGAs, and if BGA do you have a plan for soldering?

Sounds cool. I would be interested in having a board.

I've been working on the BGA issue for a while. For this project I am targeting XC3S200AN in a BGA 256-pin 1mm package. According to my tests and calculations, a 2-layer board escaping the outer 2-3 rows is sufficient. The left quadrant that connects to the 6502 has 36 pins brought out, requiring a few to come out the bottom. The RAM is the right quadrant; top and bottom quadrants connect to the expansion bus. 24 pins on top and 24 on the bottom is easy; 32 is certainly doable.

I am targeting about 3 square inches of PCB, 1x3 horizontally with expansion along the top and bottom edge, to fit a breadboard or wing adapters depending on how the expansion headers are populated.

ANs require only two power supplies (1.2V and 3.3V), and contain a flash, making them self-contained and requiring fewer support hardware.

2 layers is generally not acceptable for FPGA work, but in this case it's more than enough as we are working with a few megaherz. Also, since most of the bottom layer is used only for power and only 2 supplies are present, I can use massive conductors and decouple sufficiently well for the frequencies expected.

Philosophically, I need this board to be simple and 80's. Every FPGA board with a CPU I've seed does it backwards - the CPU is used to feed the FPGA, configure it, and even clock it. Here the board is hosted by the FPGA, configured via JTAG with no possibility of stupid problems. Having worked with PICs and AVRs enough, I can't imagine relying on these things to configure my board. It's bad enough to deal with USB flakiness on the computer end - the last thing I want to do is go looking for the AVR Dragon or some other debricking equipment to 'set fuses' on the chip responsible for communication and configuration of the board.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

I like the sound of this!

Are you including the 1.2V and 3.3V regulators on the board ?

Looks like both 128Kbyte and 512Kbyte SRAMs have 32 pins - any particular reason to go for the lower capacity?

Which of the pins are you leaving unconnected ? I assume the NC (pin 35) and PHIO1 (pin 3) pins, correct ? On the 65816 those pins have a more useful function, so if you connect those as well, the same board could host a 65816 device.

OK, that's what I was hoping to get in terms of feedback...

I think I will put a PLCC socket in (it's about a dollar for smd versions) and connect all the pins, allowing for either 65c02 or 816 to be inserted (or nothing for a general-purpose FPGA with SRAM board. On another note, it's almost impossible to find an FPGA board with an SRAM - they all put in DRAMS which require awful controllers and ridiculous worst-case latencies when a refresh cycle overlaps an out-of-order access. OK for massive RISC chips with prefetch units, bad if you are trying to be cycle aware ).

(BigEd)Looks like both 128Kbyte and 512Kbyte SRAMs have 32 pins - any particular reason to go for the lower capacity?

128KB has to do with my inventory, as does the choice of the 200AN FPGAs. I also have a bunch of 700ANs in 484 BGA form, which provides even more fpga stuff and is perhaps easier to interface as more pins are available in the outer rows - all data pins can be escaped on to top surface (with 200AN I have to bring a few vias out of the left quadrant to keep it neat). I oven-bake them with 100% success rate so far. 0.5mm QFPs are also at 100% in my previous boards. It will be interesting to bake 3 chips of different kinds at once - I've only done BGAs one at a time so far.

The only problem with BGAs is to keep them in position while baking. Carrying the board around and the vibration from the oven door closing can knock the BGAs off the pads. I am working on a positioning template that holds the FPGA in its location, a metal brace that fits into 3 or 4 holes at diagonal corners, holding the FPGA to better than 0.25mm accuracy. Possibly a fairly massive one that spreads the heat evenly around the top of the FPGA. I have some experiments to run with a batch of boards that should arrive this week.

(arlet)--Are you including the 1.2V and 3.3V regulators on the board ?--
Originally I kept the regs on a separate board to make the board more oven-friendly. I will leave footprints for two 1117s are on the back side of the board as it should be more convenient. I can hand-solder them in separately along with the decoupling caps on the bottom. It works out nicely as all the power distribution is on the solder-side anyway

I've been trying to use gEDA after being fed up with Eagle, but it stinks too. Why are all PCB layout programs such crap? It can't be that hard to do it right. In particular, why are footprints treated any differently from a board layout? Why can't I have a library of little board chunks that's easy to incorporate into a larger board? Every package I've tried is really stupid about keeping libraries of symbols or footprints. gEDA at least stores everything as text, so you have some ability to generate or mess with footprints... But it's impossible to move tracks once they are down, so moving a chip a little is a monumental task. Maybe it's back to Eagle, as much as I like opensourced stuff.

Perhaps it's time to make a PCB system in Squeak/Pharo smalltalk. If only I had more time...

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

I've done plenty of boards with the reflow oven that have double sided SMD. I do the back side first, typically populated with caps, ESD protection and other small stuff. On the second run, I populate the top side with the big IC's. The small components on the bottom are kept in place by cohesion forces from the tin. Only occasionally do components fall off, and they're always things like heavy inductors with ferrite cores.

That's encouraging. I was always too scared to flip the board and shove it back into the oven.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

One of the many demos I tried when I was shopping for CAD many years ago was Eagle, and they said it absolutely will not crash like other CADs. Well, the demo itself crashed. I had gotten very proficient at my previous job with OrCAD but it had more bugs than an ant hill, and I had written up a small book of complaints, at the request of the engineering manager, so I knew OrCAD was out. After evaluating quite a few packages, I narrowed my choices down to Maxi-PC which was a little under $2K and Easy-PC Pro which was only $375. The cash-strapped company got me the cheaper one. It's not fancy, but I've found ways to do many things with it that it probably was not initially designed to do, partly because it's simple and doesn't try to second-guess my intentions and tell me I can't do this or that. This was before Gerber 274X came out, but when I learned 274X, I found it's pretty easy to edit the Gerber files with a text editor to do more things and make it more foolproof for PCB manufacturers whose CAM people are foreigners who can't read a clear read.me instruction file and do what it says when you have complex layers that used to require multiple merge files in the days of Gerber 274D. I've done some very dense and complex boards (up to 500 parts and 12 layers) with it. Supposedly it can even do blind and burried vias, although I've never tried that. Easy-PC Pro had a lot of bugs initially too, but Number One Systems listened and cleaned it up pretty well; but then they kept adding more and more features that were of no value to me (like an autorouter that's nowhere near as smart as a human--autorouters are not the way to get good density anyway--, simulation, etc.), and making it somewhat less friendly too, so I quit taking the updates.

I've been thinking I should look into the gEDA you mention. What's wrong with my old CAD? Very little actually. Drawing arcs can only be done on 45° increments. Having the thru-hole and SMT legends separate such that only the thru-hole ones actually get printed on the board adds a little work. The number of trace widths and pad widths and pad lengths are slightly limiting so I have to plan things carefully at the start of a project, and I can't put SMT parts at random angles (39° for example), but it's no biggie. It is a bit time-consuming to do the 274D-to-274X conversion on a complex layer that's partly ground plane and partly other things for example, but that's only at the end of the project, and if I did it often enough to justify the learning curve of another CAD package, I'd also be faster at the conversion. Instead of using the supplied footprints for various components, I have made all my own which are tweaked for higher density, and I do not look forward to re-making hundreds of components in a new CAD. Moving chips and tracks as you mention is super easy though. I do use gerbv from gEDA to view what I've done in my gerber edits to make sure I got what I wanted before it goes to the board house. Edit, 12/1/16: I see there's a free 3D online gerber viewer at http://mayhewlabs.com/3dpcb .

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

(I had an idea for a cunning plan, but I want to present it as a hack on the board you want to make rather than an attempted diversion of your project: use the empty CPU socket to bring out an extra 8 or 24 data bus bits, to allow for a 16 or 32 bit CPU in the FPGA. The extra 1 or 3 SRAMs would have been piggybacked somehow onto the existing RAM, to reuse the address and control pins. Unfortunately that's a different proposition if it's surface mount RAM, which on reflection it probably is.)

It's still do-able, assuming SOJ packages. You straighten out the pins so they go down over the pins of the SRAM IC below them to be soldered. I'll try to post a picture later.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

With at least 48 IO pins I envision, you could always stick wider memory on top of it... I am, for this project, happy with 8 bits and 128KB rams. Perhaps a slightly different design would make more sense, with wider RAMS, but it's another story.

Perhaps I should make a wire-wrappable module for the Xilinx FPGAs, even if it brings out 100 pins or so... That would make it possible for everyone to mess around with the FPGAs using the glorious wire-wrapping technology from the last century.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut