Hello,

I'm currently assembling a parts list for my first SBC. I have been following schematics of other members (and non members) online, and have a decent idea of the layout and schematic that I'm looking for. One area that did not match however was the decoding logic. I have no experience in this area, and didn't find much information online. I decided to keep things simple, and let the upper 4 bits of the address space define the logic points. I sketched out my proposed decoding logic, and hope that someone can provide feedback.

Memory Map:

0000 - CFFF RAM
D000 - DFFF I/O
E000 - FFFF ROM

*edit* Adding address table to add to the logic:


Please see attached image for schematic.

Welcome!


section in the primer: http://wilsonminesco.com/6502primer/addr_decoding.html

Your RAM must have phase 2 brought into the write-enabling. (Maybe you're doing it in another circuit you're not showing.) Since RAM tends to be a lot faster than ROM, you can optionally bring the phase 2 into the RAM's select logic instead which may simplify things without slowing the system down.

A couple of things to address: You have A14 and A15 going into an AND gate for the RAM (and that going into another AND), which means both A14 and A15 will have to be high to enable RAM, meaning that to start, you won't get any RAM outside the C000-FFFF area. Also, inverting A12 before going into an AND for ROM select will exclude the range of F000-FFFF, and you'll definitely need that, at least for the vectors.

Also, enables are mostly active-low, probably because NAND and NOR gates tend to be faster than AND and OR gates.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Consider using 16k rom, so you can install systems like EhBasic.

Thanks Garth,

I found the link very useful. There's a lot to think about, but so far it's been a big help. Phi2 and WE / OE for ram will be addressed in a more complete schematic. I addressed the problems you pointed out, and only had to add an extra logic gate to make things fit. As per your article, this is still probably over complicated.

I took your suggestion for integrating Phi2 into select. I added it to the other select lines as well.


Dajgoro, I am hoping to do most of my programming in CC65. I also have (lofty) goals of someday adding an MMU to the system so I wanted to save as much space as I could for memory.

Most 65-family I/O ICs can't have phase 2 in the chip selects. The selects have to be valid and stable a certain amount of time before phase 2 goes up. And since ROM tends to be slower, letting it get started before phase 2 goes up helps get a greater system speed from a given ROM speed, so you won't generally want it there for ROM with a 6502 system (although you do for a 65816 system). IOW, just bring phase 2 into the RAM select, not the others.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

OK I removed Phi2 from the other select lines. Thanks again.

Ah, CC65 i am still trying to figure out how to make it boot from rom properly. Now i am in the phase in constructing a new cpu board with an memory mapper(sorta mmu) and dma.
How are you planning to boot your cc65 programs into ram?

Looking at the sbc-2 schematic, i can see that phi2 is only integrated into the r/w signal and not in the chip select. I followed that schematic when building my sbc and it works. So if i didn't miss something on the schematic that means that when phi2 is not active, the ram actually reads on a write cycle(but for a very short amount of time).

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

As mentioned previously I removed the Phi2 signal from the other select leads. I like your use of quad input gates BDD.. it simplifies the logic count.

I plan to use 74AC logic as recommended. Initial speed will be 1 or 2 mhz. I will probably pickup the quad logic gates however to mimic your sbc1 setup.

Building logic gates is a bit tricky for me to keep track of in my head so far. Is there an easy way to bump up your I/O select logic to 512 bytes per increment?

The R/W qualification circuit looks simpler as well. I am using the WDC 65C02 processor.

What are you using for a memory mapper?

For booting purposes I plan to follow an approach others used of having a simple terminal program that connects via serial cable. Programs will be uploaded and then executed until something more permanent is designed.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

I use the 74LS612, but somebody here called it "old silicon".
It fits my needs, so i decided to use it.
I bough it form ebay, here is the item:
http://www.ebay.com/itm/1PCS-SN74LS612N ... 33772b1fc2

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

An xc9536 or xc9572 cpld can be used as a memory mapper, since they are cheap and run on 5V.