I would encourage communication that's gracious and helpful to those who are new at this. POINTYDESMO was no doubt trying to translate the figure he had into MIPS, and compare to what the actual hardware limit might be.
My rule of thumb is that 6502 MIPS is generally 1/4 of the clock frequency in MHz. This will vary, depending on what you're doing. 6502 MIPS are worth more than most other 8-bit processors' MIPS though. I have developed some products with PIC microcontrollers, and find that the processor core in the PIC generally takes twice as many clocks to do a job as a 6502 takes, if the job is small enough that the PIC can do it at all. Both are available in 20MHz. My now possibly outdated info says that WDC has a licensee running a W65C02SB-type core at 50 MHz. This means an interrupt latency of 140ns, not including time to finish the current instruction.
By the way, a relatively new part of the
www.6502.org website has a detailed set of information on 6502 instructions. These cover the old NMOS versions, but not any of the CMOS, which have more instructions, bugs fixed, and quirks removed. As I looked through it, it reminded me again why I don't use the NMOS types. There is one part though that needs correction: It says that a bus cycle is two clock cycles' time, and that where the data sheet says an instruction takes two cycles, it's actually four clock cycles. This is not the case. All the instructions take two to seven actual clocks. For example, at 1MHz, LDA # takes 2us. Commodore briefly made a 10MHz 65CE02 in the late 80s that actually had about 30 op codes that executed in a single clock, ie, 100ns @ 10MHz.
Garth
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