Regarding timing constraints

Looking at the thread again... Timing constraints are just that - constraints and have nothing to do with the language. Since fpgasm uses xilinx tools to route I don't see why you can't add a constraint file... I will check it.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Does every element have to be hand-placed? That would be tedious, for a large clump of control logic like in the 6502.

It is modular. Each instance is placed inside the module relative to the module. (Just like RPM constraint )

Just an example:
Inside 6502 maybe Registers at 0,0, PC at 0, 10 ALU at 5 0 etc.
Inside PC, 8 2-bit counters at 0,0 0,1 0,2 etc.
EDITED:
Each module controls location of instances inside it, so the task is localized.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Another option for low-level FPGA hacking is to use the FPGA editor. Here's a tutorial. You can start out with an existing Verilog/VHDL design, and then open it up in the FPGA editor to see how it's implemented, and to make changes. I haven't used it myself yet, but I'm planning to try it on my next FPGA project. My plan is to start with a really trivial design, and use the FPGA editor to understand the slice structure better, and see what synthesis produces.

The FPGA editor is also a useful tool when you want to make a simple design change, such as experimenting with IODELAY or DCM parameters without having to resynthesize the whole design.

Of course, the FPGA editor is also a useful companion to fpgasm hacking, as you an visually inspect what your code produces.