I've embedded my comments in your post, quoted below:

One of the Steves (Jobs or Woz, I don't remember) said the 6502 was in fact chosen for the Apple because of its low cost. But I would have to add the high power-to-complexity ratio to the list of attractions.

Jack Crenshaw is a respected authority in embedded programming. In an article in the 9/98 issue of Embedded Systems Programming, he talks about different BASICs he used in the 70's and 80's, and said the 6800 and 6502 always seemed to run them faster than any other processor. (I believe the 80 family was running at higher clock speeds too.) Quoting two paragraphs:

"To me, the 8080 and Z80 always seemed to be superior chips to the 6800 and 6502. The 8080 had seven registers to the 6800's two (plus two index registers). The Z80 added another seven, plus two more index registers. Nevertheless, I can't deny that, benchmark after benchmark, BASIC interpreters based on the 68s consistently outperformed those for the 80s.

"The biggest problem with the 68s was that they had no 16-bit arithmetic. Though the 8080 and Z80 were basically 8-bit processors, at least they had 16-bit registers (three for the 8080, eight for the Z80), and you could actually perform arithmetic in them, shift them, test them, and so on. You couldn't do any of these things with the 6800 or 6502, which is one reason I still don't understand, to this day, how the 68s could outperform the 80s in benchmarks."

==========
I think this may have been a misstatement on his part. The 6801 had two accumulators, though it had only one (16-bit) index register. It also had a zero-page mode. I don't think this differs substantially from the 6800. you could do 16-bit arithmetic on the 'D' register, which was the a and b registers concatenated into a single accumulator.

==========
(End of quote) After learning the 65C02's instruction set and bus usage, I remember being impressed by the relative inefficiency of the 80 families, including the greater number of clocks the 80's needed to carry out instructions, the lack of decimal arithmetic and implied compare-to-0 in various instructions, and so on.

Don't let those clocks fool you. The Z80, for example, though it executed the same number of similar instructions in about the same amount of time used a clock that, for similar operations, had to be 3x the speed of the comparable 6800. The 6502 overlapped some execution time with bus fetches, so it gained a little over the 6800 at the same clock rate. You might find it interesting to look at the relative execution times of certain instructions common to both, then look at the instruction sets in contrast and see where each can be exploited to perform better at some things than the other.

The obvious reason WOZ chose the 6502 was that it was faster than a 6802 at the same clock rate, AND it allowed the use of the enhanced instructions that benefitted the video bitmap manipulations, AND it used a clock compatible with the notion of sharing memory with the video refresh task, thereby effortlessly supporting dynamic memory refresh.

Since then I've used PIC microcontrollers for a couple of products. The attractions include lots of I/O options, on-board everything, low price, easy programmability, and they're available off the shelf at many distributors. But the one thing I absolutely hate about them is their RISC microprocessor core that Microchip touts as being so wonderful. Compared to the 65C02, it's decrepit. The limitations require all kinds of programming jerry-rigs to get around, and then I find that if the job is small enough for them to do it at all, they take twice as many clocks to do it as a 65c02 core would take.

I'm not enamored of the PIC's either, but I do very much like the SCENIX SX, which runs at clocks of 50, 75, and 100 MHz, with only one clock tick per instruction. The architecture is VERY similar to the small PIC, except that it has an eight level call stack. See <www.ubicom.com> (its new name). I think you'll be pleasantly surprised.

Uli

>I think this may have been a misstatement on his part. The 6801 had
>two accumulators, though it had only one (16-bit) index register. It
>also had a zero-page mode. I don't think this differs substantially
>from the 6800. you could do 16-bit arithmetic on the 'D' register,
>which was the a and b registers concatenated into a single
>accumulator.

==========

I did wonder if he meant you couldn't shift the X and Y or what. Certainly you can test them; but he also did not tell exactly when this was compared to when the 6801, 6809, etc. or the 65c02 or '816 came out. Of course since then, market pressures have driven more performance increases in the 86 family than in the 65 family. Nevertheless, the latter remains a very attractive solution for some applications.

_________________
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"I did wonder if he meant you couldn't shift the X and Y or what. Certainly you can test them; but he also did not tell exactly when this was compared to when the 6801, 6809, etc. or the 65c02 or '816 came out. Of course since then, market pressures have driven more performance increases in the 86 family than in the 65 family. Nevertheless, the latter remains a very attractive solution for some applications. "

You can do arithmetic (inc, dec, add, sub, etc. but I don't think shifts and rotates are in the picture. In fact, I'm not certain you can shift/rotate the "D" register.

I would find the R65C02, particular the fast versons, which I do like very much, more attractive if they were still in prodution and for sale from a legitimate distributor.

I've found the claims that WDC is selling a 20 MHz part or even the 14 MHz part that's on their site, completely unsupported. Their IP core would be more attractive if it were availabe in a speed grade reasonable for current technology. That would mean something in excess of 100 MHz. A core that runs at 10% the speed of available technology is pretty lame. Now, don't forget that a 4-bit adder would take 4 cell delays, so if you use current 1.25 GHz technology, it's still on the order of 4 ns for the add/subract, which you have to do twice to get 8 bits processed, and since you have to do that twice per cycle, it's 20 ns plus several more cell delays to allow for routing and steering. 100 MHz, though very challenging, should be readily attainable. Moreover, since you're building the core, there's no reason you have to have all those wasted idle cycles that the 6502 had. There will be some you still have to do, but, if you organize the core (with its internal program store) such that you execute each instruction in the minimal time, there will be a reduction in the number of cycles you use up.

Anyway, that's for another discussion.

Uli

GARTHWILSON wrote:
One of the Steves (Jobs or Woz, I don't remember) said the 6502 was in fact chosen for the Apple
because of its low cost. But I would have to add the high power-to-complexity ratio to the list of
attractions.

Woz had planned his computer (the Apple I) on paper, around the 6800. However, he couldn't afford one. Then he saw the sheet on the 6502, and how it was close enough to the 6800 that he could use it instead, and it was priced so low that he could afford to buy a couple of the chips. He had liked the 6800 because it was much more like the mini computers that he knew at HP than the 8080.

Exegete AKA Roy Miller
Faith Orthodox Presbyterian Church
Apple ][ forever!

>I would find the R65C02, particular the fast versons, which I do

>like very much, more attractive if they were still in prodution and

>for sale from a legitimate distributor.

All WDC's 6502's now are the W65C02SB. The B means they have the bit-manipulations instructions I think you're looking for that Rockwell had. The non-B version has been phased out.

>I've found the claims that WDC is selling a 20 MHz part or even the

>14 MHz part that's on their site, completely unsupported.

How did you try them? Someone is selling a C64 accelerator board that runs at 20MHz with WDC parts. I haven't seen one myself. WDC says they've qualified on the Sentry 21 standard tester running up to 20MHz. I would expect standard hobbyist construction to start giving problems above 10MHz. At the higher frequencies, I would avoid the large DIPs altogether. WW PLCC sockets are available from MacKenzie Berg, through Allied. The PLCCs along with the WW sockets don't give you power and ground connections that are a whole lot shorter than what you get with DIPs; but you get more of them, reducing the overall inductance where it's most critical; and the longest lines on your breadboard can be made shorter because the parts can huddle closer together than they can with the large DIPs.

Then I would use a breadboard with planes on both sides, so you can use the bottom for ground and the top for +5V. With thru-plated holes, the power pins can be soldered in and a chip bypass capacitor can be soldered right at the base of the pin with no extra lead length. (You could do this without thru-plated holes too, but any movement of the socket could break the chip capacitor.) Such breadboard is available from Vector for over $100 for a 7" x 10.6" piece. Having worked in RF power MOSFET applications engineering at up to 1200 MHz in the mid-80's, I understand more about stray inductance than I otherwise might. A circuit that expects to support a good 20MHz square wave will need to be well-behaved up to at least a couple hundred MHz. Otherwise the resultant ringing, groundbounce, and so on can easily keep a home-made project from working at high speeds. I can tell you from experience that the world is a whole lot friendlier below 200MHz. Many of our friends on 6502.org will have inexpensive 20MHz dual-trace oscilloscopes, but few will have the 250MHz+ 'scopes necessary to see which way the bear went into the woods when inadequate construction practices are keeping their fast new baby from working at all.

The workbench computer that I use all the time has 4 and 6 MHz parts, and 70ns memory. It happens to work at 7MHz, although obviously it's not guaranteed to. It has been adequate for most of my workbench needs, but my next one will be ready for much higher speeds as the parts become available. If you want to run a 6502 at 20MHz, you'll have a phase-2 high time of 25ns. If the data set-up time to read memory is 8ns, that leaves you with 17. If you have fast RAM-enable glue logic of only 5ns, that means you'll have to have memory that's 12ns or better. Anything worse than these numbers will have to be made up somewhere else. If you had trouble getting WDC parts to run at the advertised speeds, my suspicion is that what was inadequate may have been a combination of the construction and the logic and memory speeds, not necessarily a WDC part.

This discussion area started out being for 6502 C compilers, but has evolved quite a bit. Does anyone mind? Maybe we should take it up under a different discussion name.

_________________
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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The email editor here stinks! I wish I could go point-by-point ... <sigh>

> How did you try them?

Well, I didn't try them, though I emailed the WDC folks at a time when I had a solid application for their part. I tried every source and agent I could contact and nobody I could find had ever encountered a 65C02 from WDC, least of all one of the fast ones they claim to make. It does no good that they're making the parts, if, in fact they are, if they won't sell them.

The Rockwell 65C02 instruction of which I'm fondest is the indexed indirect jump, by the way, though the bit manipulations are also handy.

I believe I agree about the package size, and, since all my prototype boards are made as you describe, ground plane on the wiring side and power plane on the component side, with a grounded strip around the outside so one can easily ground a scope or L.A. probe, though I had mine made with dry-film solder mask so I don't have to worry about solder problems. If I need to attach bypass, I normally use a .01 uF or 220 pF cap right at the leads. It's about as good a power distribution scheme as one could want. I've used standard DIP's in this package and managed frequencies as high as 16 MHz without difficulty. The board helps a lot with power<=>ground noise, and I've had circuits on these boards with well over 100 flipflops all driven from the same clock operating quite reliably.

High frequencies are a problem sometimes, but I see no reason to be afraid of them. Of course there are few classical applications that require them. Most control and communication tasks can be managed just fine at modest frequencies well under 100 kHz, so they can be accomplished easily with a 1 MHz CPU. What's interesting to me, however, is to see how much can be done with lots of speed rather than lots of resources.

I've heard talk and read email, etc, about the fast WDC parts, but I don't know anyone who's actually bought them. If you have a proven source, please share it with me. I have some goodies that I'd like to try running on a fast 65C02. One is I'd like to bit-bang a floppy disk and possibly a hard disk interface. I think that would be interesting, since it would be limited only by the programmer's ability. One should easily be able to read any format without worrying about the controller.

Now, about that timing with a "20 MHz 65C02" if one could believe it to exist, I do believe the margins are a mite more generous. First of all, addresses settle during Phase-1, well before the rising edge of Phase-2. From the standpoint of memory timing, however, that should be of no concern whatever, since almost everyone has cache memory lying on the floor of the closet on an old '486 board that uses 8,10, 12, or 15 ns cache. All you have to do is transfer the contents of your EPROM to the SRAM before switching from 2 to 20 MHz. Today's inexpensive GAL's will decode, switch, count, etc, at speeds well in excess of 150 MHz with pin-to-pin delays on the order of <5 ns.

The trouble with getting WDC parts to run at 20 MHz is simply in getting WDC parts. I've experienced no other difficulty. So far, the 2-micron Rockwell parts I've got are the fastest I've used, and the timing I see with them suggests they'd routinely run 2-3x as fast as they're rated. I may have to give that a shot sometime.

I find it's easier, with a 65C02, to use a RAM disable rather than enable. An I/O select disables the RAM, so it's normally enabled. I'm not sure why that works better than driving the enable selectively on memory select. It does, of course, make for fewer transitions on that signal.

I'm working some retrocomputing problems (repair, etc) with old Z80 stuff from time to time, and once that's done and working right, I'm looking to try to translate the CP/M OS from PL/M to 'C' for purposes of trying it out. I've never tried to translate a working piece of software from one processor to a completely different sort of CPU, though I have translated to 650x from 680x. Back in the early '80's I had a multiple processor development system that used a Z80 running CP/M as the system I/O processor, and as the master processor for Z80 development as well. When another processor wanted disk I/O, the Z80's console input buffer was loaded over the shared bus, and the Z80 was awakened while the requesting processor released the bus. When he was done, the Z80 relinquished the bus so the disk buffer could be accessed. It was nice being able to use a single OS console interface for all the processors. If I had to do that again, I'd change a few things, but probably not the OS.

Uli

You can buy the parts directly from WDC. I have some PLCC's here I bought a year or two ago, but I still haven't done anything with them. They're marked for 10 and 16 MHz. Getting them was quick and easy, as long as you don't mind the $100 minimum order. My orders from Jameco, Mouser, Digi-Key, etc. seldom end up under $100 when I order other parts. WDC sells the PQFPs too, which are a lot smaller than the PLCCs. Both have two Vdd pins and four Vss pins.

About the 20MHz 6502 timing: The RAM CS logic must have phase 2 brought in to make sure you don't enable the thing before R/W and the addresses are completely valid, or allow address or data to begin changing before R/W is solidly back in the R camp (high state) at the end of a write cycle. Otherwise you risk writing garbage, or writing to a wrong address. So while you can set up the address earlier, the enable time will have to be shorter. According to their timing diagram I have here, R/W does not wait for the address to be valid first-- it changes at the same time, both coming and going. I have found errors in WDC's timing diagrams though, and it would be welcome news if R/W were actually timed such that phase 2 could be left out of the glue logic.

_________________
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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I find both of the statements you make regarding the WDC device quite surprising. First of all, I've made numerous fruitless attempts to contact the WDC people via email, just to get budgetary pricing on their 14 MHz parts (which are the fastest they assert in their data sheet). How does one make contact? Would it work better if I wrote them on my letterhead?

It's also surprising that you've found timing inconsistencies with their datasheet. I can imagine that there might be some data hold time or address hold time discrepancies, but the way I remember their part being spec'd it's obvious that something's got to be wrong. They take a signal that they call Phase-2 (IN) and produce a Phase-1 and Phase-2 output. Their timing seems to suggest that the prop-delay of their inverter to Phase-1 from Phase-2(IN) is zero, and we know that can't be the case. Moreover, the setup and hold time spec's for data are muddled somewhat, actually suggesting that there's only a 20 ns window around the falling edge of Phase-2 (and It's not clear whether that's IN or OUT) during which data is actually valid. Clearly, one has to look at the part to see what's really there.

I suspect this is mainly specsmanship, where WDC has endeavored to claim all the available headroom for its own protection. In any case, I'd suggest that since the CS prop delays, which are longer on most RAM's than the OE prop delay, suggests that one should use the input clock to gate the write strobe, while one uses the output Phase-2 to gate the read enables. These spec's also don't address the effect of assymetry on the clock.

I'm concerned about one assertion you make, namely that R/w is valid before the remaining controls. That is very much contradictory to their spec. I'd venture that this can be worked out by further examination of the relationship between the clock (IN) and (OUT) relationship. Unfortunately, I don't have their spec in front of me at the moment, so I can't investigate further. I'm just looking at the table on their web page <www.westerndesigncenter.com/chips.html>.

One can't dispute that it would be difficult to design with the spec they've presented. I seriously doubt that it would be as difficult to design with the real part, however, having debunked the spec they publish.

I guess I'll have to send them a written inquiry about budgetary pricing so I'll know what it would cost to use their part in a "real" design. I'm not terribly impressed with their IP spec, so I'd probably not choose to use it. There are, after all, open (free) HDL models of the 6502 core out there that claim to perform as well as theirs. With a reasonable amount of work at least one of those could be speeded up considerably. Besides, I'd rather build my own.

Uli

> How does one make contact? Would it work better if I wrote them on

> my letterhead?

I just called them up with credit card in hand, said "Give me five of this, five of that, and seven of the other..." and a few days later, they arrived.

> It's also surprising that you've found timing inconsistencies with
> their datasheet. I can imagine that there might be some data hold
> time or address hold time discrepancies

I believe one of the hold times on write is specified to be 0, which will never in actuality be the case. I don't remember what the exact spec. was off the top of my head. The one I'm working right now though is the bank address set-up time on the data bus on the '816 before phase-2 goes up. The way it's spec.ed, the fastest parts would not work if the timings did not exceed the spec.. I E-mailed the person at WDC who used to answer these questions, but I just found out he's no longer there and I should re-send the E-mail directly to Bill Mensch.

> something's got to be wrong. They take a signal that they call
> Phase-2 (IN) and produce a Phase-1 and Phase-2 output. Their timing
> seems to suggest that the prop-delay of their inverter to Phase-1
> from Phase-2(IN) is zero, and we know that can't be the case.

I think there was a commercially-made computer 20 years ago that had problems because of this assumption. I don't remember what it was. I think it's much better to call the phase-2 input "phase 0" to avoid the falacy you mention.

> I'm concerned about one assertion you make, namely that R/w is
> valid before the remaining controls. That is very much
>contradictory to their spec

not _before_, but rather at the same time accroding to the spec.s I have here, making for a precarious situation since, for example, the amount of capacitive load on R/W may be different from that on other lines, skewing something forward or back a few ns, etc..

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I have, wonder of wonders, received a reply from WDC, though they've carefully sidestepped my questions about budgetary pricing. I'd order some parts if they weren't so close-to-the vest with pricing, since that smells bad. I don't like to leave open issues for discussion on the phone. I prefer the written record that email gives me.

What did your 16MHz-marked part cost? I'm completely unwilling to buy any of the peripherals that don't run at the top-rated speed, and, in fact, since they don't drive much, I prefer to use the parts I'd otherwise use to buffer the peripherals in place of the peripherals. That means using latches or clocked registers instead of tristate buffers, but that's no issue. It works out well, though.

I'll be interested to see what the timing of these devices really looks like as the oscillator speed is ramped up.

Uli

I goofed. The 816's are marked for 14MHz, not 16. They were $6.18 each for five. The 65c02S (before the "B" version) were $5.07 each for five. These were both in the PLCC package, which may or may not affect the price-- I didn't ask.

Garth Wilson

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

It's a good thing to keep in mind that the '816 is not a 65C02 of any kind.

I guess I'll have to ask about the DIP parts.

Uli

For using assembly language in an embedded control application, the W65c02SB would usually be better; but the Forth kernal I wrote specifically to take advantage of the 816's 16-bit registers runs nearly 3x as fast as my semi-optimized Forth for the 65c02 at a given clock speed. To say it was closely related to the 6502 would be an understatement; but with the newer 02 versions filling in the rest of the op code table differently from how the 816 does, the 816 can't run newer 02 code.

I didn't ask about DIPs because I don't want to even try to get them running cleanly at 10MHz and up. PQFPs are available too, but highly impractical unless you get multilayer boards made. I've done many extremely dense MLBs, but so far not for these processors.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

There's good reason why you've not done that. They are suitable for the most part for resurrecting existing firmware, but other than that they're suitable only for mental masturbation projects. The only thing they offer is tremendous speed at relatively low cost.

Uli

WDC definitely has a 8 Mhz 65C02 part. I'm holding it right now
in my hand.

It's labeled:

W65C02S8P-10
SA9444A

Maybe it's 10 Mhz?

I've noticed that WDC's website no longer seems to be up.
Anyone know what happened to it?

Toshi