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 Post subject: Re: POC Computer
PostPosted: Thu Aug 02, 2012 4:51 pm 
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Tor wrote:
Wouldn't the improvements to the filesystem remove the possibility to read or write a disk (or image) in Linux? Having the ability could be useful. 14-char filenames are very painful when you operate on large filesystems (and yours will be much larger than what the original S51K used to handle), so that improvement (and the others) are very understandable of course, but it seems you may also lose something in the process too (although I imagine at least the filename size increase is something that could easily be incorporated into a patched Linux filesystem variant).

-Tor

Your question is a good one and is about something I have contemplated in my design (BTW, your question also shows that you read most, if not all, of my diatribe :D). At this time, I'm not particularly concerned with being able to interface to a raw Linux disk or image. The point of this exercise is to develop a working environment, not to wire in interoperability with another operating system.

As an aside, my modified S51K filesystem will not be using the same magic number as the real S51K, so the door is always open to being able to read the genuine article at any time, if I choose to do so. Support for multiple filesystems would require that the data describing the filesystem geometry and access sequencing be separated from the code that manipulates the filesystem. Right now, it'll be more convenient to not do this until I have a working system. However, I have sketched out the methods by which such a thing could be accomplished.

A "feature" of my modified S51K filesystem is that it will not be using linked lists to manage data block and inode allocation/deallocation, as is done in the genuine article. Linked lists were a way to deal with the relatively slow disk access and compute-bound performance of the PDP hardware that Thompson used for much of his seminal development work. Again, he demonstrated some very clear thinking in doing it that way, and was able to achieve a good compromise between efficient disk space utilization and real-time performance.

However, contemporary hardware's compute-bound performance is such that an allocation bitmap is more efficient and less demanding of MPU time to search for and locate an unallocated block or inode (this applies to the 65C816, even at the relatively modest 10 MHz Ø2 clock rate I'm using in POC V1). Using 16 bit reads, writes and shifts to scan and manipulate the bitmap control words will help in this regard. For example, a 16 bit LDA <addr> comes with a one clock cycle penalty, due to it actually being back-to-back eight bit accesses, but is about 60 percent faster than LDA <addr> followed by LDA <addr+1> to read a word. So I anticipate substantially less compute-bound activity to manipulate the bitmap than I would see with manipulating linked lists.

Further to this performance angle is the fact that I have arranged the filesystem in a way that guarantees that bitmap structures will stored in contiguous disk blocks. Although it can't be done in the POC V1 unit due to its modest 52 KB of RAM, I will be able to read the entire inode allocation map into core in a single disk access in the POC V2 unit, since there will be enough RAM to support a large number of block buffers. The modified S51K layout will be configured with 64K of inodes. The matching allocation bitmap (IAM) will span eight logical blocks, or 16 physical blocks, which is 8 KB en toto. With POC V2's 1 MB of RAM, I can keep the entire IAM in core for a protracted period, which means that a disk access to retrieve the IAM doesn't have to occur every time a new file is created or an old one is deleted. A sync daemon would periodically write out the IAM when it becomes "dirty" so filesystem consistency is maintained.

The data block allocation bitmap (BAM) will be too big to be loaded en masse into core. However, I also have an algorithm worked out that will assist the kernel in figuring out which BAM block points to an unallocated data block, so only the relevant bitmap block is fetched when a data block is to be allocated. Once that block is ensconced in a buffer it can stay there as long as other buffers are available for use. The net result of this is that as a file is being written and data blocks are being allocated, the bitmap image is being manipulated with minimal disk accesses. This was something that wasn't particularly practical on the old PDP machines due to small core size.

In considering the idea of support for other filesystems, something worth noting is that the ext... series of Linux filesystems are effectively modifications and extensions of the basic S51K structure, with elements drawn from the Berkeley filesystem (BFS). This is also true of the AFS and EAFS filesystems that were widely supported in the SCO UNIX 3.2... series. So support for them could be provided as well. Again, it's primarily a case of separating the data from the logic, something that I'll eventually address when I have built hardware that can support pre-emptive multitasking.

------------------------
Fixed a typo that resulted in "core" becoming "code."

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Last edited by BigDumbDinosaur on Fri Aug 03, 2012 6:57 pm, edited 1 time in total.

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 Post subject: Re: POC Computer
PostPosted: Fri Aug 03, 2012 9:59 am 
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BigDumbDinosaur wrote:
In considering the idea of support for other filesystems, something worth noting is that the ext... series of Linux filesystems are effectively modifications and extensions of the basic S51K structure, with elements drawn from the Berkeley filesystem (BFS).[..]

I was an early tester (aka "guinea pig") of the ext filesystem that Remy Card wrote for Linux. In that variant he used linked lists, but lessons learned was that it lead to fragmentation (and, I think, also performance issues, but that part is only from memory because I don't think any of that correspondence made it into easily searchable online storage), and so he changed to bitmaps for ext2 (it's interesting in itself that he learned so much from the first 'ext' filesystem implementation that all the improvements implemented in ext2 were so good that the filesystem is holding up well even today. Sounds good for _your_ V2 project! :))

-Tor


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 Post subject: Re: POC Computer
PostPosted: Fri Aug 03, 2012 9:06 pm 
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Tor wrote:
I was an early tester (aka "guinea pig") of the ext filesystem that Remy Card wrote for Linux. In that variant he used linked lists, but lessons learned was that it lead to fragmentation (and, I think, also performance issues, but that part is only from memory because I don't think any of that correspondence made it into easily searchable online storage), and so he changed to bitmaps for ext2 (it's interesting in itself that he learned so much from the first 'ext' filesystem implementation that all the improvements implemented in ext2 were so good that the filesystem is holding up well even today. Sounds good for _your_ V2 project! :))

-Tor

It's interesting that you mention the fragmentation issue, as it was mostly a non-issue on the comparatively tiny disks that existed when the S51K filesystem was developed. There just wasn't enough storage to matter. BTW, the Acer filesystem (AFS) that was developed some time after S51K went into widespread use dispensed with the linked lists and went with bitmaps. The extended Acer filesystem (EAFS) had the same feature, along with support for longer filenames. In another bit of irony, when Commodore developed their first floppy disk drive (c. 1978), it too used a bitmap for the BAM. That basic arrangement carried through the entire Commodore floppy drive line, right up to the 1581 3½ inch unit.

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Last edited by BigDumbDinosaur on Sat Aug 04, 2012 7:25 pm, edited 1 time in total.

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 Post subject: POC V1 Filesystem
PostPosted: Sat Aug 04, 2012 7:20 pm 
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I started a separate topic on the filesystem I am developing for POC V1, so as to not dilute this topic too much with software matters.

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 Post subject: Re: POC Computer
PostPosted: Mon Aug 20, 2012 6:18 am 
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BigEd wrote:
Hi BDD
is any of your firmware source available? If not, do you expect to publish it in the future?
Cheers
Ed

Ed, I posted the entire BIOS ROM listing on POC's website. Select Downloads and you'll see it. The file size is about 550KB (ASCII) and 11,700+ lines. This listing is ROM 0.8.1 and contains all planned features except one with which I'm still tinkering. Once that feature has been coded and debugged, the ROM will officially become version 1.0.0 and, barring the discovery of more bugs, will probably not receive further development. The next ROM will be for POC 2 when it gets built. Just about everything in POC V1's ROM will be transferable with little alteration.

Here's a synopsis of all the features of POC V1's ROM:

  • 100 percent native 65C816 operation. Except for a few lines of code at the beginning of the reset routine, the 65C816 is run in native mode, using 16 bit operations where beneficial. I made extensive use of 816-specific instructions, especially in number processing.

  • Buffered and interrupt-driven serial I/O. Port A is the console port and port B is the auxiliary port, presently used as a data link to my UNIX development box. Both ports can be run at up to 115.2 Kbps.

  • Checkerboard memory sizing and testing. The tests include detailed scans of the zero page and stack areas before the POST display is enabled. Once POST is enabled the absolute memory count is displayed as testing progresses, just like on a "real" computer. :-D

  • Interrupt-driven SCSI support. The SCSI subsystem implements all useful SCSI-1 features and a few SCSI-2 features. I did not implement tagged queuing and disconnect/reconnect, due to insufficient ROM space.

  • BIOS primitives jump table. The jump table, starting at $00E000, includes entry points for console and auxiliary port byte-at-a-time I/O, reading and writing the timekeeper, SCSI command execution, character string output to the console, reading or writing NVRAM, etc.

  • Initial system load (ISL) capability. Following POST and SCSI enumeration, the BIOS will attempt to load the boot block from the boot device (SCSI ID $00) and execute master boot code, if present. Master boot will then attempt to load and execute a stage 1 boot loader that can ultimately start an operating system. There is also space in the boot block allocated to setting up a filesystem table (four filesystems maximum per disk). Master boot does not look at this table—that's the job of the stage 1 boot loader.

  • Uptime counter, programmable delay timer and alarm. I did the uptime counter early on as part of the exercise to get the Dallas watchdog to generate jiffy IRQs—the UT counter proved that the watchdog was not merely sleeping in his house. The UT counter is also handy for gauging the stability of the system (longest uptime to date has been 73 days).

    Originally, I created the alarm to deal with a potential "no IRQ" issue with the 53C94 controller, but I have since found it useful for other purposes. I experimented with several implementations before settling on the present version, which isn't necessarily the final version.

  • NVRAM support. The Dallas watchdog has 256 bytes of NVRAM available for any use. I use it to store the primary and secondary boot device IDs, the time zone (the clock itself is set to UTC), default console and auxiliary port BPS, and some other data. There's a 16 bit checksum to verify that valid data exists. Due to a lack of space in the BIOS ROM, an external program has to be loaded and run to change NVRAM, or to set the date and time.

  • Intelligent console support. I devised a macro language that can be embedded in any text string to execute console procedures, such as clearing the screen, addressing the cursor, and so forth. There are also commands to change display intensity, enable reverse video and draw box graphics, the latter which I put to work in displaying the POST screen's banner.

  • Machine language monitor. The monitor was scratch-written to use the 65C816's native mode and 16 bit registers. Monitor features include:

    • A - Assemble code.
    • C - Compare memory areas.
    • D - Disassemble code.
    • F - Fill memory.
    • G - Execute code.
    • H - Search memory for pattern.
    • J - Execute code as a subroutine.
    • L - Load code (see below).
    • M - Dump memory.
    • R - Dump MPU registers.
    • T - Copy memory to memory.
    • V - Display ROM version.
    • Z - Clear console screen.
    • > - Change memory.
    • ; - Change MPU registers.
    • ! - Execute SCSI command. Commands include:

      • F - Format unit.
      • I - Reset SCSI subsystem.
      • R - Read block(s) from unit.
      • S - Read sense data from device.
      • W - Write block(s) to unit.

    • Ctrl-D - Soft-reset system, similar to a PC's three-finger salute.

    The F and T commands are implemented with the '816's MVN (block copy) instruction, resulting in incredibly quick response. SCSI commands are entered as:

    Code:
    !<cmd>

    followed by whatever parameters are required. For example, to read from a SCSI device, one would enter:

    Code:
    !r <ID> <LUN> <LBA> <NBLKS> <BUFFER>

    where:

    Code:
    <ID>      SCSI device ID, $00-$07
    <LUN>     SCSI logical unit (usually zero on most devices)
    <LBA>     Logical block address, zero-based
    <NBLKS>   Number of blocks to read (512 bytes per block with disks and tapes, 2048 with CDs)
    <BUFFER>  Where the blocks will go

    In addition to the above commands, the monitor has a built-in number conversion feature. Typing a number in binary, octal, decimal or hex will display that number in all four bases, e.g.:

    Code:
    +49151
      $BFFF
      +49151
      @00137777
      %1011111111111111

    All numbers are internally represented by 32 bit integers. Addresses and instruction operands may be entered as 8, 16 or 24 bit values in any base, although POC V1's architecture doesn't decode addresses beyond $00FFFF. Depending on the instruction, it is possible to assemble code with a 24 bit address, e.g.:

    Code:
    LDA $123456,X

    although the address' MSB ($12) will not result in access to RAM bank $12, since there is no bank other than $00. Also, since the '816 has dual-sized registers, an instruction such as:

    Code:
    LDA #$8F04

    is legitimate. Entering:

    Code:
    LDA !#$21

    will assemble as:

    Code:
    A9 21 00  LDA #$0021

    a feature referred to as "force long immediate" (FLIMM) in the ROM listing comments. Without the !, the instruction would be assembled as:

    Code:
    A9 21  LDA #$21

    This also works for the .X and .Y registers. Plus you can also do something like:

    Code:
    BIT !#$21

    which will assemble as:

    Code:
    89 21 00  BIT #$0021

    Of course, you could also enter it as:

    Code:
    BIT !#%100001

    and get the same result. Hex is the default radix if no radix is entered.

    The data loader (L) takes a Motorola S-record input stream from the auxiliary serial port, converts it to binary, checks for errors and writes to the appropriate location in memory. During the load a progress indicator is printed to the console and when done, the starting and ending addresses to which the load occurred are displayed. Normally, loading occurs to the address in each record, but can be changed for the entire load by entering a page offset, e.g.;

    Code:
    L $04

    The above would add $0400 to all load addresses, wrapping around if the resulting address exceeds $FFFF. The loader can process S0, S1, S5 and S9 records—the computer sending the S-record data must transmit <EOT> as the last character to terminate the process. The loader can deal with CRLF or LF line endings, making it compatible with S-record files created in either Linux/UNIX or DOS/Windows.

    All of the above is crammed into an 8KB ROM space. There are only 81 bytes in the ROM that are unused.

    By the way, any resemblance between this monitor's features and those of the Commodore 128's resident monitor wasn't coincidental. :-D The C-128's monitor was well-designed (unusual for CBM—they must've purloined Jim Butterfield's SuperMon :lol:), and other than adding the SCSI commands and S-record loader, as well as extended addressing support, I didn't see any need for any functional improvement. The monitor's code is not a copy, however, as the '816 is sufficiently advanced over the 6502 to warrant starting with a blank canvas.

As published, the ROM listing can't be assembled unless edited to get rid of the stuff added by the assembler. However, before someone starts writing a sed script to do so, you should know that when the ROM reaches version 1.0.0, my next task will be to disassociate the machine language monitor from the rest of the ROM and make it available for anyone who wants it. As written, all source code is tailored to the Kowalski assembler, with extensive macro usage to adapt to the '816-specific instructions. To make it easier for someone to assemble the code outside of the Kowalski environment, I'll eventually generate a version that will be compliant to WDC's assembler syntax standards and as devoid of macros as possible.

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Last edited by BigDumbDinosaur on Mon Aug 20, 2012 10:55 pm, edited 1 time in total.

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 Post subject: Re: POC Computer
PostPosted: Mon Aug 20, 2012 10:00 pm 
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Excellent, thanks!


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PostPosted: Tue Aug 21, 2012 6:59 am 
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If anyone is interested in experimenting with a 65C816-powered SBC, I have enough parts on hand to build two more copies of POC V1. I can furnish the unit ready to run, or as a "kit" (pile of parts—everything is through-hole except the SRAM and MAX238, the former being SOJ-32 and the latter, SOIC-24). In either case, a tested ROM and complete documentation will be included: schematics, board layout (both EPCB files) and the source code for the ROM, all on a CD. For a listing of all ROM features please read this post.

Also, I can furnish a SCSI host adapter (HBA) if wanted. The HBA plugs into the RTC/expansion socket on the mainboard and supports any 8 bit SCSI device (maximum of 7). 16 bit devices can be connected to the SCSI bus with a standard bus adapter. The BIOS will auto-detect the presence of the HBA and any connected devices, and enable the SCSI driver if at least one device is accessible.

POC V1's hardware specifications are as follows:

  • W65C816S microprocessor.
  • 128 KB static RAM, 52 KB addressable.
  • 32 KB ROM, 8 KB addressable.
  • Dual TIA-232 serial interface ports (RJ-45), simultaneously capable of 115.2 Kbps with custom programming (set to 38.4 Kbps in the BIOS ROM).
  • Real-time clock (RTC) with calendar and alarm.
  • Expansion port.
  • 74AC glue logic.
  • Powered by 5 VDC, 250 MA maximum, from any PC-AT or PC-ATX power supply.

POC is stable at 12.5 MHz with the RTC plugged into the expansion port socket, and 10 MHz with the SCSI HBA installed (the RTC is then plugged into the HBA).

For a console you will need an ASCII terminal that is or can emulate a WYSE 60, WYSE 150 or WYSE 160, or compatible terminal emulation software running on Linux, a Mac or Windows. The terminal connection is via TIA-232 and requires that hardware handshaking be employed.

POC's auxiliary serial port can be connected to another computer for the purpose of transferring data via the BIOS ROM's built-in S-record loader. Hence you can write software on a Linux, Mac or Windows box and send it over to POC for testing. This is how I developed and debugged much of the code in the BIOS ROM.

If you are interested in this offer please contact me via the forum's private message facility.

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PostPosted: Fri Aug 31, 2012 4:36 pm 
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During foraging in my old parts storage, I came across an 18 GB Seagate Barracuda LVD SCSI disk that I had pulled out of a server some years ago. I also found a 68 pin wide cable that I had customized with an active terminator, evidently to allow me to connect an LVD disk (which does not have onboard bus termination) to a single-ended SCSI port.

On a lark, I decided to hook up this combination to POC and see if it would fly. It does, and POC's SCSI BIOS enumerates the disk, says that it can be addressed with a 32 logical block address (LBA) and correctly reports its capacity as $02245CDC or 35,937,500 physical blocks. Block size is reported as $0200 or 512 bytes, so the formatted disk capacity is 18,400,000,000 bytes.

This particular drive runs at 7200 RPM and its average latency is about 50 percent shorter than the old Seagate Hawk I was using (5400 RPM), plus track-to-track seek time is much better. So the theoretical throughput is higher, but is still limited by how quickly the MPU can shuffle bytes hither and yon. Even with the SCSI bus only running at the asynchronous rate of 3.5 MB/second, the disk is much faster than the computer. It's usually the other way around. :lol:

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 Post subject: POC Computer
PostPosted: Sun Sep 02, 2012 4:44 am 
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BigDumbDinosaur wrote:
This particular drive runs at 7200 RPM and its average latency is about 50 percent shorter than the old Seagate Hawk I was using (5400 RPM), plus track-to-track seek time is much better. So the theoretical throughput is higher, but is still limited by how quickly the MPU can shuffle bytes hither and yon.

I was at a client's location yesterday to replace a drive in their server with a higher capacity unit. The drive I removed is a 73GB Seagate Cheetah that runs at 10,000 RPM and has only two years of service on it. I may try it out with POC to see if the lower latency has any discernible effect, although I would be surprised if there was one. Testing with 48KB loads from the Seagate Barracuda drive currently attached, which spins at 7200 RPM, produced an average transfer rate of 497KB/second. As all of these LVD drives have full track buffering, the latency would only matter on the first access, as succeeding accesses to the same LBA would load from the buffer. So I'm reasonably certain that the 497KB/sec rate is probably as fast as it is going to go. Reduced latency and seek time will help, of course, during random accesses, which are more typical of drive operation in the average system.

While on the subject of tinkering with hardware, I also received an NXP 26C92A DUART yesterday that I had ordered a while ago. The 26C92 has better timing specs than the 2692A with which POC was originally equipped, has a couple of extra features (interrupt steering being one of them) and is software- and pin-compatible. Due to the 26C92's better timing, especially the /CEN (chip enable) response time, I decided to amp up Ø2 and see if she'd go or blow.

  • With the SCSI host adapter (HBA) installed, 10 MHz is the maximum speed at which stability is assured, primarily due to bus loading by the HBA (a limitation I hope to avoid in POC V2 with aggressive bus drivers).

  • With the HBA removed but the 2692A still installed, POC can run with stability at 12.5 MHz.

  • After replacing the 2692A with the 26C92, I found I could increase Ø2 to 15 MHz and have stability, as long as I used an AMD 27C256-55DC EPROM (55ns access time). With a ST Micro 27C256 (70ns), POC would randomly lock up at 15 MHz (no surprise there).

For now, the 2692A will suffice, as I can't take advantage of the 26C92's capabilities in the present design. I will use the 26C92 in POC V2, mostly because of its ability to steer IRQs to different pins, rather than converging all of them on a single output as is done in the 2692A. While its faster timing is nice, the 26C92 isn't fast enough to run at 20 MHz without wait-states.

By way of explanation, the CPLD will have eight interrupt inputs, of which two are assigned to the watchdog and SCSI controller. With the 26C92 I can divvy up DUART interrupts to several CPLD inputs. The result is when the DUART interrupts, the resulting IRQ number generated by the CPLD will localize the code, avoiding the need to test all possible DUART interrupt sources. This should substantially decrease execution time in the part of the interrupt service routine that takes care of the DUART. That's the theory, anyhow. :D

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PostPosted: Wed Sep 19, 2012 6:09 pm 
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One of the devices I have connected to the SCSI bus is an old Hewlett-Packard DDS2 tape drive, which has a native capacity of 8GB per cartridge. While POC's BIOS recognizes the drive at boot time there was no support for it in the BIOS, mostly because I didn't have a copy of the SCSI specs for stream (i.e., sequential access) devices. I finally got hold of a copy and have augmented the BIOS so I can erase and rewind a tape, as well as read from and write to it. The BIOS version is now 1.1.2.

Once I got this tape stuff working I wrote a simple copy tape to disk program to see how well it would run, using block at a time transfers, that is, each transfer moved 1024 bytes. Ultimate performance, of course, is determined by how fast bytes can be copied from the tape to the tape drive's internal buffer. Most DDS2 drives can manage a theoretical 1MB/second from an uncompressed tape, assuming no CRC error correcting is required on individual blocks. More often than not, the transfer rate ends up being about 80 percent of that, mostly due to CRC corrections that occasionally have to be applied. As POC can achieve a real-time transfer rate to the SCSI bus of 497KB/second using a 32KB transfer size, it's clear that the tape drive can stream data nearly twice as fast as POC can process it.

Timing the "copy tape to disk" program over a period of five minutes produced an effective throughput of 220KB/second. The apparent performance disparity vis-a-vis raw SCSI throughput makes sense, in that each write to the disk must be preceded by a read from the tape, requiring that two complete SCSI transactions be executed for each 1024 bytes transferred. When the transfer size is under 8KB, the overhead in the SCSI protocol (bus arbitration, selection, etc.), as well as the POC's SCSI driver primitives, becomes a significant part of the total processing time, explaining the relatively low throughput.

In a practical tape archiving program, a relatively large buffer size would be used to reduce the number of SCSI transactions, resulting in higher sustained throughput. A SCSI function that reads certain drive parameters (e.g., optimal streaming size) can be used to "tune" for the optimum buffer size. The H-P specs for this particular drive recommend a 32KB transfer size per SCSI transaction. Accordingly, I reassembled my copy program to transfer 32KB per SCSI transaction, and saw the throughput over a five minute period rise to 310KB/second.

POC V2 will have 1MB of RAM, so large buffer support will practical.

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 Post subject: Re: POC Computer
PostPosted: Wed Sep 19, 2012 6:27 pm 
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Hi BDD
Is the hardware such that you could write to disk at the same time as reading the next block from tape (or vice versa)?


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 Post subject: Re: POC Computer
PostPosted: Wed Sep 19, 2012 7:13 pm 
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BigEd wrote:
Hi BDD
Is the hardware such that you could write to disk at the same time as reading the next block from tape (or vice versa)?

Unfortunately no.

SCSI doesn't support multiple "listeners" on the bus (to borrow an IEEE-488 term). Each transaction starts with POC, acting as an initiator, telling the tape drive, acting as a target, to read a block. During that transaction, the bus is busy, which precludes any other device from connecting. Once the block has been read, POC initiates the write to the disk, which will now be the target. Again, the bus is busy during the write, preventing a command to read the next block from being sent to the tape.

The SCSI command protocol includes a COPY command that can cause a device other than the host computer to act as an initiator and transfer data to another device other than the host computer, e.g., from disk to tape. However, COPY is not implemented on many SCSI devices, as it was declared to be an optional function by the ANSI T10 committee. Were COPY available, then throughput would approach the raw bus speed of 5MB/second.

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 Post subject: Re: POC Computer
PostPosted: Wed Sep 19, 2012 7:15 pm 
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Ah, thanks.


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 Post subject: POC Computer
PostPosted: Wed Nov 07, 2012 12:38 am 
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Location: Midwestern USA
I haven't been doing much on this as of late. Unrelated projects, plus several RFQs for new computer systems have kept me quite busy. The timing of the RFQs is a bit awkward for me, as I'm supposed to start scaling back my business operations right about now. However, both are for long-time clients and I would not feel right telling them I'm not interested.

Meanwhile, POC V1.1 is just sitting on on the desk, running and being a good boy. The uptime counter right now is 66.7 days (5,760,433). I guess one could call that "stable." :D

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Last edited by BigDumbDinosaur on Wed Nov 07, 2012 4:21 am, edited 1 time in total.

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 Post subject: Re: POC Computer
PostPosted: Wed Nov 07, 2012 2:47 am 
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Congratulations. That's a success for 1.1!

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