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 Post subject: POC Version 2
PostPosted: Thu Jul 19, 2012 4:21 pm 
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Balance of illustrations attached.

Attachment:
File comment: POC V2 Schematic Page 6 — RAM, ROM & I/O
poc_v2_p6.gif
poc_v2_p6.gif [ 52.04 KiB | Viewed 1163 times ]
Attachment:
File comment: POC V2 Schematic Page 7 — External Interface
poc_v2_p7.gif
poc_v2_p7.gif [ 38.59 KiB | Viewed 1163 times ]
Attachment:
File comment: POC V2 Printed Circuit Board Layout
poc_v2_pcb_rv1.0.jpg
poc_v2_pcb_rv1.0.jpg [ 1.59 MiB | Viewed 1163 times ]

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 Post subject: Re: POC Version 2
PostPosted: Thu Jul 19, 2012 5:24 pm 
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Hi BDD
please would you be so kind as to post a tabular BOM to help identify each IC on the PCB without squinting at the schematics?
Thanks!


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 Post subject: Re: POC Version 2
PostPosted: Thu Jul 19, 2012 7:54 pm 
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Did you use export the image using 300 pixels per inch? Nice detail!

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 Post subject: Re: POC Version 2
PostPosted: Thu Jul 19, 2012 8:58 pm 
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BigEd wrote:
Hi BDD
please would you be so kind as to post a tabular BOM to help identify each IC on the PCB without squinting at the schematics?
Thanks!

"...squinting at the schematics?" Are they too small? I can upload larger versions if you think it would help.

Anyhow, attached is an illustration of the PCB with ICs and some other parts called out. Eventually I will finish the BOM and add it to the schematic pages.

ElEctric_EyE wrote:
Did you use export the image using 300 pixels per inch? Nice detail!

Thanks! I used 300 to generate the raw JPEG and then reduced it to 144 with progressive scan to make the file smaller and appear to load faster.
——————————————————————————————————————————————
EDIT: Added a second illustration of the PCB with mechanical dimensions.
——————————————————————————————————————————————
Attachment:
File comment: POC V2 PCB w/Major Parts Locations
p128001_poc_v2_pcb_rv1.0.jpg
p128001_poc_v2_pcb_rv1.0.jpg [ 1.52 MiB | Viewed 1148 times ]
Attachment:
File comment: POC V2 PCB Mechanical Dimensions
p128002_poc_v2_pcb_rv1.0.jpg
p128002_poc_v2_pcb_rv1.0.jpg [ 419.64 KiB | Viewed 1147 times ]

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Last edited by BigDumbDinosaur on Thu Jul 19, 2012 9:59 pm, edited 1 time in total.

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 Post subject: Re: POC Version 2
PostPosted: Thu Jul 19, 2012 9:14 pm 
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Thanks - that's very nice, even more informative than a BOM in some respects.
Can you say something about the 28-pin DIP expansion port?
Cheers
Ed


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 Post subject: Re: POC Version 2
PostPosted: Thu Jul 19, 2012 11:47 pm 
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BigEd wrote:
Thanks - that's very nice, even more informative than a BOM in some respects.
Can you say something about the 28-pin DIP expansion port?
Cheers
Ed

The "expansion port" is actually the socket that the watchdog timer (WDT) plugged into in POC V1. When I decided to cobble together a SCSI host adapter, I patched POC V1 to bring the additional signals needed to the WDT socket so I could piggyback the host adapter to the existing board. Later on, I added more signals to take care of the 53C94 SCSI controller's DMA functions, necessitating that I build an updated version of POC V1 with all patches incorporated into the unit. This led to me deciding to change the WDT's socket to "expansion port," although it doesn't have enough pins to carry all needed signals to act as a true expansion port.

POC V2 is going to have IRQ priority capabilities, so each device capable of interrupting the MPU will do so on its own line, and the CPLD will, in turn, pull the MPU's IRQB input if the interrupting source has been enabled. Hence the expansion port has been augmented to provide the WDT and 53C94 with independent IRQ lines. The expansion port signals are as follows:

Code:
A0-A4   Buffered address bus.
D0-D7   Buffered data bus.
/DPWR   WDT power supply control output (currently unused).
/IO1    WDT chip select ($00D100).
/IO2    53C94 SCSI PIO chip select ($00D200).
/IO3    53C94 SCSI DMA FIFO enable ($00D300).
/IO4    53C94 SCSI DMA acknowledge ($00D400).
/IRQ1   WDT IRQ output.
/IRQ2   53C94 IRQ output.
/KS     WDT power supply control input (currently unused).
/RD     Read data, inverted MPU RWB output qualified by Ø2.
RST     Active high reset to 53C94.
/WD     Write data, MPU RWB output qualified by Ø2 & HMU write-protect logic.

With the above signals, plus Vcc and ground, all 28 socket pins are spoken for. I've toyed with the idea of using a 32 pin socket, but think I'm pushing things as it is. :lol: The host adapter effectively takes the buses off-board, and while the 74ABT buffers can drive pretty hard, I'm not sure just what I'm faced with at this point with distributed capacitance.

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 Post subject: POC Version 2
PostPosted: Fri Jul 20, 2012 8:27 pm 
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In mentioning the "expansion port," I should also mention that ultimately I want to build a 65C816-powered beast that would implement a true expansion bus with accessory card slots. This contraption would be my "final design," which in addition to the expansion slots, would have the SCSI HBA incorporated into the "motherboard," as well as provisions for accepting 4 MB plug-in memory modules to allow up to 16 MB total to be installed. I like the way Garth designed his DIMM (other than the pins :)) and if possible, would like to use it.

However, before designing the "final design," I'm going to test Garth's DIMM on POC V? (probably the next iteration in the POC series) to see what effect its presence in the circuit will have at 20 MHz operation. As I have an H-P 1725A 'scope (275 MHz) at my disposal, I can easily see what the DIMM's loading does to signal transition times.

The "final design" "motherboard" will be laid out to conform to the micro-ATX standard and thus will be mountable into almost any PC enclosure. It will be powered from a conventional ATX power supply through the 20 or 24 pin motherboard power connector, with power on/off working as it does in modern PCs. The expansion slots would be conventional 32 bit PCI sockets, which are readily available and are designed for 33 MHz operation in their original application.

All of this, of course, is in the future.

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 Post subject: Re: POC Version 2
PostPosted: Fri Jul 20, 2012 9:01 pm 
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Why SCSI vs SATA for drives and USB for everything else? SCSI is pretty much un-represented today at the consumer level I think.


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 Post subject: Re: POC Version 2
PostPosted: Sat Jul 21, 2012 2:14 am 
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whartung wrote:
Why SCSI vs SATA for drives and USB for everything else? SCSI is pretty much un-represented today at the consumer level I think.

  1. If you can find an SATA controller chip that can be directly interfaced to a 65xx-style bus I'm sure a lot of people would like to know about it. Anyhow, I have lots of SCSI hardware at my disposal: disks, tapes, DVD drives and controller chips (53C94). Why not use it? Also, SCSI disks (especially) are very robust and reliable high performance devices. At best, SATA hardware is designed to be cheap. Despite all the SATA hype, SCSI continues to be the choice for high quality servers where maximum I/O throughput is required. My company does not ship servers with SATA disks and tapes. We do use SATA DVD drives because they generally don't see a lot of use in server duty. We can supply a SCSI DVD drive if required.

  2. USB is much less robust and flexible than TIA-232, TIA-422 or TIA-485. Almost anything that sends/receives data can be adapted to one of these standards using inexpensive chips that are easy to attach to a 65xx bus—the NXP 2692A DUART in POC V1 is such a device. Can you say the same thing about USB?

    Also, USB is downright feeble when it comes to transmission distance. TIA-232 can go 150+ feet with reliability on CAT3 cable. TIA-422 and TIA-485 can go thousands of feet if the communications rate will not exceed 100 Kbps. Any of them can go miles with short-haul modems. Fifteen feet is the outer limit feet with USB.

  3. I'm not building a consumer product. :lol:

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 Post subject: POC Version 2 Update
PostPosted: Thu Sep 20, 2012 7:05 pm 
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Continuous work on my filesystem design (as well as real, revenue-producing work) has pushed POC V2's design to the back burner, so to speak. However, the burner is lit and I periodically shift gears and work on V2 for mental variety. I've been fiddling with the code for the CPLD and have gotten a preliminary scheme concocted, which compiles and simulates on an Atmel 1508AS. With one exception, all glue logic will be implemented in the CPLD, which in addition to substantially reducing the parts count in the design, gives me the flexibility to fiddle with things like wait-stating and memory protection.

One of my ongoing quests is that of trying to get a real DMA controller (DMAC) working to handle SCSI bus transfers. It may be possible to simulate a DMAC in the CPLD if enough macrocells and product terms are available after all other logic functions are handled. As the 1508AS has quite a bit of capacity, and since it has enough pins to connect to the entire address bus, as well as the MPU's RDY and BE inputs (the latter to tri-state the buses during DMA), I've got a vague idea on how to make the CPLD also handle the DMAC role. I need to learn more about how DMA controllers work, but I have enough of an understanding right now to at least outline the required operations and sequencing. It helps that the 53C94 SCSI controller is designed for DMA operation, which should simplify the synthesis of a DMAC when I get to that point.

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 Post subject: POC Version 2 DMA
PostPosted: Sun Sep 23, 2012 6:55 am 
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I keep getting a burr under my saddle about not being able to do real DMA on my POC unit during SCSI I/O. Currently I do "pretend DMA" by having the MPU poll the 53C94 SCSI controller's DREQ output for a "ready" (logic high) state and then having the MPU read or write the DMA FIFO. The hardware itself is quick enough, but I can't do anything about the rate at which the MPU can copy bytes from point A to point B. I've squeezed the read/write loops so tightly blood is oozing out of them, yet at 497KB/second (more-or-less), the sustained transfer rate is only about 14 percent of the SCSI bus' capability when running in SCSI-1 asynchronous mode (3.5MB/second), which is the slowest of the three bus speeds supported by the 53C94. Even if I were able to step the Ø2 clock up to 20 MHz, I'd see, at best, about 875-900KB/second—at least one wait-state would be required to access the 53C94.

The 53C94 is capable of running the bus at the SCSI-2 synchronous speed of 10MB/second, which all SCSI hardware made in the last 15 years is able to support. Naturally, real-time throughput isn't going to be the same as the raw bus speed, due to various limitations in the attached devices (e.g., the DDS2 tape drive is good for about 1MB/second when streaming). Disks, of course, are much faster—the one I have connected to POC is capable of an off-the-platters transfer rate of 28MB/second. Since disk access will be the most frequent activity, it's no surprise that I'm leaving a lot of performance on the table, an unavoidable consequence of my "pretend DMA" really being just a form of PIO. The answer, of course, is to use a DMA controller (DMAC).

I've looked at the Intel 8237 and Freescale (Motorola) 68440, both of which are still available, and have concluded they aren't the answer. Adapting either of them to the 65C816 bus would be non-trivial (especially the 8237), and neither would be able to stay with the '816 when running at 20 MHz—they too would have to be wait-stated. Wait-stating a DMAC is obviously counterproductive, which thinking has led me to the idea of making a "homebrew" DMAC that will interface to the '816's bus with a minimum of hassle and be able to run at the same Ø2 clock rate as the '816. If I could concoct such a device I'd be able to close in on the raw SCSI bus performance.

On the face of it, a DMAC has a relatively simple job to do. The device is basically a deliveryman who drives a really fast truck (or lorry, for our UK friends), never crashes, always obeys traffic signals and always delivers the goods to the right place. A DMAC has to read a byte from the source when it has one, write a byte to the destination when it is ready to receive one, maintain a count of bytes transferred, stop when the required number of bytes have been shifted and let the MPU know when it's finished. If an interrupt has to be serviced, the DMAC has to be able to temporarily suspend its activities, stopping for a traffic light, as it were. None of this involves logic of the sort that requires an ALU or other microprocessor-like intelligence. It's simple counting, reading and writing. All of this sounds to me like something that could be synthesized in a reasonably powerful CPLD.

In my application, the only time DMA activity would be required is during SCSI I/O. Either a byte is being copied from the DMA FIFO in the 53C94 to RAM or a byte is being copied from RAM to the DMA FIFO. The key aspect of this arrangement is that only RAM has a variable address—the DMA FIFO is statically addressed in the I/O block. Therefore, only one address register is required in the DMAC for a functional implementation. As counting and address incrementation are required, a state machine will be required to turn the CPLD into a DMAC.

From a hardware standpoint, the DMAC would need the following connections:

  • Address and data buses.

  • DREQ. This is a high true input that is driven by the 'C94. DREQ will be asserted any time the 'C94 is ready for data (write mode) or has data (read mode).

  • /DACK. This is a low true output to the 'C94 which will be asserted to connect the DMA FIFO to the data bus when the 'C94 has asserted DREQ.

  • BE. This is an output to the MPU's low true bus enable input, which is normally held high. If BE is pulled low the MPU will tri-state the buses and its RWB output. During DMA activity, BE would be negated so the MPU stays off the buses while the DMAC has control.

  • RDY. During DMA activity this MPU input will asserted to halt program execution. When all bytes have been transferred, RDY will be released and the MPU will resume execution at whatever address is in the program counter. At the start of DMA, RDY would be asserted before BE. At the end of DMA, BE would be deasserted before RDY. This aspect of the DMAC will represent one of those interesting timing situations.

  • /IRQ and /NMI. When an interrupt occurs DMA operation will be suspended and the MPU restarted so the interrupt can be serviced.

  • /DMACE. This would be a low true input to the DMAC that would function as a "chip select" and would be used to program the DMAC. The DMAC would have virtual registers that would be addressed the same as the registers in any other I/O device. These registers would be used to set up the starting RAM address, the direction of data transfer, the number of bytes to transfer, and so forth.

  • Ø2. The DMAC would be sequenced by the Ø2 clock, so the bus speed will be the same as if the MPU were in control.

The logic flow required to perform a DMA transfer would go something along the lines of the following:

  1. The MPU sets the direction of transfer, either RAM to SCSI bus (outbound) or SCSI bus to RAM (inbound).
  2. The MPU loads the starting RAM address, which would be a 24 bit value.
  3. The MPU loads the number of bytes to be transferred, which would be a 16 bit value.
  4. The MPU tells the DMAC to start. The DMAC responds by executing the following steps:

    1. The DMAC negates RDY, causing the MPU to halt on the next Ø2 high. Effectively, the MPU will be stopped at the instruction that follows the one that told the DMAC to start.
    2. The DMAC negates BE, causing the MPU to tri-state.
    3. The DMAC takes control of the buses, as well as /RD (read data) and /WD (write data), which outputs are normally controlled by the MPU.
    4. With the DMAC now having control of the system, the following steps are executed for as many bytes as are to be copied:

      1. The DMAC waits until the DREQ input goes high, which indicates that the DMA FIFO is ready.
      2. On the next Ø2 high, the DMAC gets a byte from RAM (outbound) or the FIFO (inbound).
      3. On the next Ø2 high, the DMAC puts a byte into the FIFO (outbound) or RAM (inbound).
      4. The DMAC increments the address.
      5. The DMAC decrements the byte counter.
      6. If the byte counter is not zero, loop back to step 4.D.a.

    5. Upon transferring the final byte, the "DMAC" relinquishes control of the buses by tri-stating the relevant outputs.
    6. The "DMAC" releases BE, thus allowing the MPU to regain control of the buses.
    7. The "DMAC" finishes by releasing RDY, which causes the MPU to resume execution.

When the MPU resumes, it is likely that the 'C94 will have interrupted, since completion of a DMA transfer or a bus phase change causes an IRQ. Hence the next thing the MPU would do is prepare for the next step in the SCSI sequence.

It's entirely possible that a better way of sequencing this mess than what I described above may exist. It'll ultimately depend on how well I can implement the state machine required to move and count bytes. This gets into an area of programmable logic about which I don't have much knowledge. It'll be an interesting learning experience getting it to synthesize.

Anyone think that I'm being impractical? If this could be made to work then it is conceivable the design could be generalized to work with RAM to RAM as well as RAM to I/O, thus creating a sort of blitter whose speed would be effectively limited only by the speed of the chosen hardware.

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PostPosted: Mon Oct 01, 2012 8:59 am 
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BigDumbDinosaur wrote:
I keep getting a burr under my saddle...

Okay, now there are several burrs under the saddle and the horse is getting testy. :lol:

POC V2, as I mentioned in earlier posts, will be designed around CPLD glue logic, more RAM, prioritized interrupt circuitry and an improved way of using the 53C94 SCSI controller's DMA channel. The latter change, along with the prioritized interrupt circuitry, will require a modification to the SCSI host adapter and hence a new printed circuit board (PCB) for it. In the work I've done so far on POC V2, I've tailored the design to allow me to lay out a PCB that will fit the specifications of Express PCB's (EPCB) Proto-Pro service. A Proto-Pro board can have up to 21 square inches area, with no more that 650 holes of all types. Beyond that it is necessary to use their higher cost production service, which sets the board size limit at 12 inches by 14 inches, and essentially no hole limit. The new saddle burr is I would be placing two 4-layer Proto-Pro orders, one for the new POC board and another for the new host adapter board.

It gets a bit more interesting. POC V1 uses a WYSE 60 dumb terminal for the console, driven by TIA-232. The WYSE 60 went out of production a number of years ago and the supply of new ones has dried up. There are remanufactured units and software-compatible replacements still available, but their future is uncertain, given that the general computing spectrum has moved away from host-based systems employing serial terminals (terminals, when used, are generally thin clients that are really disk-less PCs). This has made me decide that perhaps I should consider designing an integrate console into POC V2.

Obviously, the console needs video and a keyboard. Sounds (e.g., squawks and beeps) are optional, but are handy to get the user's attention when needed. I can worry about sound later. Actually, the video part isn't too tough to implement. In another topic, there is discussion about the Picasso serial-to-VGA adapter, a device that is driven by bi-directional, TTL-level TIA-232 and produces text and/or graphics on a standard VGA video monitor. This device could be made to be the video part of POC V2's console by direct-connecting it to channel-A of the DUART. The DUART's channel-B would continue in its role as a high speed serial I/O connection to the outside world. The circuitry is very simple: RxD, TxD, Vcc, ground and an active-low reset. No line drivers are needed.

The keyboard part is a little more interesting. PC keyboards are ubiquitous and cheap, so that can be considered to be the weapon of choice. The keyboard's PS/2 interface is a serial synchronous setup, which requires bit-banging to read in data (or command the keyboard to do something), along with a decoding algorithm to turn keystrokes into ASCII codes. It's possible to do this through a 65C21 or 65C22, but that's a bit of work to properly code and also burdens the MPU with with the decoding work.

Considering all that, I decided to adapt Daryl Rictor's PS/2 keyboard interface to POC V2. Daryl's design uses an Atmel microcontroller (AVR) to handle the keyboard stuff and offload all keyboard processing from the MPU. The interface looks like an I/O device with an 8-bit data port and a two wire handshake, which presents no special problems in adaptation. Again, the circuitry is simple and due the manner in which the AVR does its work, interrupts can be used to read in and buffer keystrokes for later use by the foreground application. A separate interrupt-drive piece of code can be used for sending commands to the keyboard (e.g., turning on the Num Lock feature).

Adding the integrated console hardware would increase the mainboard's silicon population and thus take up more space, which is already at a premium, especially with the presence of the PLCC-84 CPLD and the two 512 MB x 8 SRAMs. I did a very preliminary layout and almost immediately bumped into the 650 hole Proto-Pro limit. Pushing things around and replacing some through-hole parts with SMT got me closer to meeting the hole limit, but to no avail. I even considered soldering the DUART and MPU (both PLCC-44) to the board, but decided I was getting too far off-course with the design.

After several hours of playing with this, I concluded I would have use EPCB's production service. With area and hole constraints thus relaxed, I could also integrate the SCSI hardware with the rest of the unit, eliminating the plug-in host adapter and the added bus loading it was causing. The irony is that the project will actually be less expensive and with all hardware on a single board, would result in a better performing unit that could meet one of the goals of this design: 20 MHz operation.

Naturally, this is quite a step up from POC V1, and thus could lead to some problems, especially in getting the integrated console to work right. My initial step will be to procure a Picasso VGA adapter and jury-rig it to the first design POC V1 board so I can create and test a suitable driver—it can be run out of the ROM at boot time and I don't even need a keyboard for testing. The Picasso's command set is actually quite straight-forward and I don't envision too much trouble getting it to generate a proper display. I might even be able to include some fancy graphics!

The keyboard adapter is more problematic. There really isn't any particularly good way to wire it into POC V1 for testing without designing and building an interface board that can be piggy-backed onto one of the chip sockets to gain access to the data bus and other signals. I could do such a board on the cheap using EPCB's Mini-Board service (cheapest they offer), but don't like the idea of spending yet more money on something that will be discarded once testing and debugging are done. While I may contemplate such a step, I suspect I'll just design the interface into the POC V2 board and make sure I don't make any kind of an error that will prevent it from working. If there's going to be a problem, it most likely will be in software, not the physical implementation.

Now, here's where the fun starts. :D Since I am going to layout a larger PCB, I can arrange it in such a way that it can be made to fit into a standard mini-tower PC enclosure, with the keyboard, VGA and auxiliary serial ports all in the locations where you would expect to see them. This would be a "truncated" micro-ATX layout that wouldn't have the PCB area normally reserved for the slots. A 20 pin Molex Mini-Fit Jr receptacle on the mainboard would accept a standard ATX power supply power connector, opening the door to using the "soft" power control functions in the Dallas 1511 watchdog. Also, I can connect the enclosure's front panel LEDs to the mainboard (gotta have lights, y'know), as well as the power and reset push buttons. Put the cover on it and it would appear to be a PC, until the power-on banner screen appeared. :lol:

Needless to say, this could get interesting!

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PostPosted: Mon Oct 01, 2012 5:24 pm 
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BigDumbDinosaur wrote:
BigDumbDinosaur wrote:

It gets a bit more interesting. POC V1 uses a WYSE 60 dumb terminal for the console, driven by TIA-232. The WYSE 60 went out of production a number of years ago and the supply of new ones has dried up. There are remanufactured units and software-compatible replacements still available, but their future is uncertain, given that the general computing spectrum has moved away from host-based systems employing serial terminals (terminals, when used, are generally thin clients that are really disk-less PCs). This has made me decide that perhaps I should consider designing an integrate console into POC V2.

Obviously, the console needs video and a keyboard. Sounds (e.g., squawks and beeps) are optional, but are handy to get the user's attention when needed. I can worry about sound later. Actually, the video part isn't too tough to implement. In another topic, there is discussion about the Picasso serial-to-VGA adapter, a device that is driven by bi-directional, TTL-level TIA-232 and produces text and/or graphics on a standard VGA video monitor. This device could be made to be the video part of POC V2's console by direct-connecting it to channel-A of the DUART. The DUART's channel-B would continue in its role as a high speed serial I/O connection to the outside world. The circuitry is very simple: RxD, TxD, Vcc, ground and an active-low reset. No line drivers are needed.

The keyboard part is a little more interesting. PC keyboards are ubiquitous and cheap, so that can be considered to be the weapon of choice. The keyboard's PS/2 interface is a serial synchronous setup, which requires bit-banging to read in data (or command the keyboard to do something), along with a decoding algorithm to turn keystrokes into ASCII codes. It's possible to do this through a 65C21 or 65C22, but that's a bit of work to properly code and also burdens the MPU with with the decoding work.

Considering all that, I decided to adapt Daryl Rictor's PS/2 keyboard interface to POC V2. Daryl's design uses an Atmel microcontroller (AVR) to handle the keyboard stuff and offload all keyboard processing from the MPU. The interface looks like an I/O device with an 8-bit data port and a two wire handshake, which presents no special problems in adaptation. Again, the circuitry is simple and due the manner in which the AVR does its work, interrupts can be used to read in and buffer keystrokes for later use by the foreground application. A separate interrupt-drive piece of code can be used for sending commands to the keyboard (e.g., turning on the Num Lock feature).



Another option is Vince Briel's PockeTerm (http://www.brielcomputers.com/wordpress/?cat=25) - either as is, or you might consider integrating something similar into your own design.


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PostPosted: Mon Oct 01, 2012 7:00 pm 
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rwiker wrote:
Another option is Vince Briel's PockeTerm (http://www.brielcomputers.com/wordpress/?cat=25) - either as is, or you might consider integrating something similar into your own design.

That site appears to be dead.

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 Post subject: Re: POC Version 2
PostPosted: Mon Oct 01, 2012 7:23 pm 
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Joined: Fri Aug 30, 2002 1:09 am
Posts: 8510
Location: Southern California
Maybe it was just down for a hiccup. Try again. I didn't have any trouble. Looks interesting.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?


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