6502 or ARM core selection?

[BigDumbDinosaur]

BTW, I just catching up on my reading and replying here. Nearly three months of being sick and unable to pound on the keyboard has put me way behind the eight ball.

[GARTHWILSON]

Quote:

Going beyond two-layer is where the cost starts going up more because they have to make multiple thinner boards and then laminate them together.

The cost differential is coming down and square inch for square inch, a four-layer board is about 60 percent the size of an equivalent two-layer design. The advantages go well beyond physical size. Four-layer designs, in which the inner layers handle power and ground, are potentially a lot less noisy, generally allow increased component density (you're not having to use up space for power and ground runs) and greatly reduce voltage fluctuations and ground bounce, the latter which sabotages a lot of designs.

Yes, and although I've said that many times before, I should have repeated it. (Don't forget to count the set-up charge though, as it is probably independent of board size.)

The tendency is to think that the ground plane is to reduce the DC resistance of the return, and to think that the ground plane allows the return current to take the shortest possible path. Instead, what happens is that the return current through the plane takes the shape of the trace above it whose current it is returning. The equal currents running in both directions right near each other cancel out that trace's inductive reactance and its antenna effect. A "pour" does not qualify since the current can't get through interruptions in the copper. It has to go around, and then you have a big loop again, like a coil. In fact, that's exactly how some cell-phone antennas are made-- running the trace over a cut in the ground plane.

Quote:

I did my POC unit on a four-layer board and it proved to be stable at 12.5 MHz (maximum speed the I/O hardware would tolerate). In fact, in a fairly recent test, I removed all the decoupling capacitors and it still was stable at 12.5 MHz. That would be attributable to the fact that the inner power and ground layers act as a giant bypass capacitor and were able to sink most of the switching noise. However, don't take this to mean you should forego decoupling caps. Any good design will have one for each active device on the board.

I believe I read somewhere, probably in Dr. Howard Johnson's articles on high-speed digital design but I can't find it now, that two parallel plane layers have no inductance at all in getting the power and ground connections to all the ICs. IOW, it's the best of all worlds-- getting rid of the both the inductance and the requirement for local bypass capacitors.

[BigDumbDinosaur]

GARTHWILSON wrote:

I believe I read somewhere, probably in Dr. Howard Johnson's articles on high-speed digital design but I can't find it now, that two parallel plane layers have no inductance at all in getting the power and ground connections to all the ICs. IOW, it's the best of all worlds-- getting rid of the both the inductance and the requirement for local bypass capacitors.

I'd keep the bypass caps despite the inner layers. Nowadays it is possible to build a pretty complex design without having to use a lot of glue logic. So it's not as though you would need a bushel basket full of caps to populate your board. Also, even top-of-the-line X7R MLCC ceramics aren't very expensive. So a cost argument would be difficult to make, I'd think.

[Dajgoro]

Wee, today i finally got my first ever dev board, and my first arm core (in non consumer electronic form), an university professor made a deal with NXP so that we can buy the LPCXpresso LPC1353 board for 95 Kuna ~16$! So i quickly bought one, and now i am downloading the software environment... It also has a jtag, which can be cut off the board, and i wonder if i could use it to program Xilinx cpld?

[BigEd]

Great! Can't find an exact match (nothing bigger than 1343) but it seems likely to be a Cortex M3 at 72MHz - is that right? I don't know if you can use the header as a general jtag adapter.

[Dajgoro]

The jtag can be separated from the board, and it has the pins so you can easily solder header.
I am now trying to make a simple blink test, ill post again when i manage to get it working.

Edit: I can't find anywhere how many mips does this mcu have.

[Dajgoro]

I downloaded the newest release of the ide, and i can't figure it out!
When i follow the manual instructions, some things are not as in the manual, so ti is not helpful!
When i managed to build the application, and when i run it, it seems like it loads arm machine code into my pc's ram, and starts to execute it, and i immediately get an not a valid Win32 application error.

[BigEd]

That's not ideal! Is there any forum for this IDE? EEye has had a little success with the xilinx forums when he's had trouble with ISE.

[Dajgoro]

I started a topic on our local student forum, maybe someone knows how does it work, if not i shall send an email to the professor...I could also try to install older versions...

[Dajgoro]

The ide can't find the usb board, i tried googling, and i looked for drivers, but no luck. I have win xp sp3.

[Dajgoro]

Problem fixed! I had to manually select the drivers with the device manager, and now it works.
I tested the blink test, and it works too.

[Dajgoro]

A picture that i took when i got the module, a size comparison between the module, the 6502, and the 74ls181 alu...

6502.org wrote:

Image no longer available: http://i49.tinypic.com/2n8nf9u.jpg

[BigEd]

And the idea (if you were so brave) is that you can cut it down the middle once programmed?

In other words, the right-hand-side 72MHz ARM module with the DIP-54 size is kinda-sorta detachable?

[Arlet]

BigEd wrote:

And the idea (if you were so brave) is that you can cut it down the middle once programmed?

Yes, that's the idea. The funny part is that the chip on the left is also an ARM part, and much more powerful than the chip on the right, but it's only used as a JTAG interface.

[Dajgoro]

I won't cut it until i find a project for it...
I see there is a additional jtag header on the jtag, can i jtag the jtag with it?