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PostPosted: Sun Jun 03, 2012 12:07 am 
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All the registers made for a friend's excuse to use the 1802 for his senior project for his BSEE in 1982, because he didn't need to add a RAM IC.  In spite of all the registers though, the 1802's performance was really, really poor compared to the 6502's.

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PostPosted: Sun Jun 03, 2012 12:18 am 
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With all due respect Garth, what if the 6502 did have 16 registers like the 1802 had, with the instruction set of the 6502 while maintaining speed of the 6502? Then what would you say?

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PostPosted: Sun Jun 03, 2012 1:10 am 
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Then on my next project, I'd start looking for ways to use them to strealine my code with what their capabilities were.  Hopefully there would be added addressing modes to go with them, otherwise I'm not confident that I'd find much benefit.  Even after I daydreamed (like everyone else) about additional instructions I would like on the '02, the '816 met or surpassed most of them, growing my confidence that Bill Mensch really did a great job in planning '816 for great performance for the silicon and pin budget, based on real-life applications with higher-level languages, in turn leading to my 65Org32 idea of keeping the '816 mostly as-is but incrementally working toward extending it to 32 bits for every register (A, X, Y, S, DP, PB, DB, although maybe not P) and non-multiplexed buses.  Having several duplicate sets of the registers does sound beneficial for quickly switching tasks, even for re-entrant interrupt service in a system that is not using a multitasking OS.  I'm glad you've had the interest in delving into the HDL with the goal of extending our favorite processor.

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PostPosted: Sun Jun 03, 2012 4:12 pm 
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According to my copy of Computer Architecture by Hennessy and Patterson, chapter 2.11, register graph colouring work best with "at least 16 (and preferably more) general-purpose registers".

The RCA 1802/1804 and SWEET16 hits the sweet spot. I believe 6502 also would if the zero page was more accessible, hence my ruminations on a dual port architecture. The only snag is that the LDA (zp, x) results in half of these to be unaligned. Perhaps a LDA (zp, 2x) would overcome this and also the INX; INX that can be found in various source code.


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PostPosted: Mon Jun 04, 2012 12:33 am 
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The only snag is that the LDA (zp, x) results in half of these to be unaligned. Perhaps a LDA (zp, 2x) would overcome this and also the INX; INX that can be found in various source code.

The only real problem I can think of with two-byte addresses not being aligned is with the NMOS 6502 JMP (xxFF) bug; but that would not affect addresses in ZP (regardless of whether the addresses they point to are odd or even).  The bug was corrected on the CMOS 6502, so the only reason I kept aligning them in my Forth was, IIRC, that it made a few things easier, possibly SEE (the Forth de-compiling word), FIND, and >NAME (with names allowing the high 128 bytes of special characters as well).  Otherwise alignment didn't matter; in fact, it wasted memory.  There's a lot of INX INX and DEX DEX to add or drop whole cells in the ZP data stack though, which my old wish for a double increment and double decrement would solve.  If the bytes weren't addresses so they didn't have to be together for indirect addressing, they could be in separate spaces (like a page holding the low bytes, a page holding the high bytes, and optionally more) so a single INX or DEX or INY or DEY can move you up or down a byte pair or quad or whatever.  But having the registers and data bus the same width as the address bus as with the 65Org32 means only a single address location is needed to point to anywhere in memory.

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PostPosted: Wed Jul 11, 2012 6:19 pm 
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The EE Life section of EE Times has an article titled "Is 8 bits dying?" where 8- and 32-bits processors are compared:
http://www.eetimes.com/electronics-blogs/other/4389890/Is-8-bits-dying-

The arguments are interesting, most I guess are familiar to most here. One that I miss is ease of programming, which is why I put this comment in this thread.

One that I do not understand is that of chip floor area. It is argued that old processors are designed with old rules. Well, if these are, like ARM, designed in Verilog or VHDL, the tool chain should optimise to modern rule sets. Or am I missing something here?

Incidentally the article is a follow up on one called "Trends in embedded software design"
http://www.eetimes.com/discussion/other/4372183/Trends-in-embedded-software-design?Ecosystem=embedded
Here more strange arguments are fielded such as the need for networking required 32 bits. Odd. Networking was quite well working in the BBC model B, and TCP/IP has been implemented in other 8-bit machines. Anyway, for huge volume products networking and over the air update is not always even desirable.

For both I note extensive libraries are not put forward as an argument.


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PostPosted: Wed Jul 11, 2012 6:34 pm 
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I don't think it's saying that old architectures are necessarily built with old design rules. Rather, it's that 8-bit micros available today include offerings of old designs made on old processes (maybe run in old factories)

The article has a lot of pros and cons with no firm conclusion, but then it is aiming to predict the future!


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PostPosted: Wed Jul 11, 2012 8:21 pm 
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Each of the industry magazines is always trying to be ahead of the others by predicting the future.  In some ways they are right of course, but their mindset ignores the niches and the reasons some have for keeping a particular technology alive for decades after consumer electronics have moved on.  RS-232 is one of these that had its death certificate signed long ago, and yet it lives on in some industrial settings where it's not worth the down time to replace something that works just fine.  They might even add new RS-232 lines from time to time so the existing system that communicates over them won't need to be replaced.  There are a lot of reasons why 8-bit processors probably will never go away like 4-bit ones did.  [Edit:  This article in Electronic Design magazine supports that idea, that the 8-bitters aren't going away.]

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PostPosted: Fri Jul 13, 2012 11:41 am 
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I do professional embedded work, and the niche where 8 bit has sufficient advantage over 32 bit is getting smaller all the time. I used to work with 8 bit CPUs, but now I do everything with ARM (mostly Cortex M0/M3 nowadays). Power is just as low as 8 bit, packages are just as small, prices are lower, and development is easier. I can still see a niche for ASICs running an 8 bit CPU in very high volume, extremely low power productions for a while, though.


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PostPosted: Sun Jul 15, 2012 12:37 am 
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This is an interesting article. The decision which processor to use in an embedded computer design depends on a number of factors. Some of them are soft - like available skills. If everything runs on / everyone uses ARM, this will be it, even in applications that do not necessarily need it.

I think here it makes sense to think about a scalable architecture - one that goes from 8 bit up to 32 (or more) bits - using the same tool chain, interoperable (i.e. compatible), with an easy to learn instruction set, ...

Ok, that certainly fits my #65k extension of the 6502 up to 64bit, although I don't think that this one will win ;-) But a nice coincidence

André

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PostPosted: Wed Jul 18, 2012 9:18 pm 
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GARTHWILSON wrote:
All the registers made for a friend's excuse to use it for his senior project for his BSEE in 1982, because he didn't need to add a RAM IC. In spite of all the registers though, the 1802's performance was really, really poor compared to the 6502's.

Interesting. So I took a closer look including through the Usenet Newsgroup comp.arch which I believe should be called comp.archaeology...

Anyway, the 1802 has a few warts in terms of design.
  • I/O straight into the ISA is clever for a few things but sure eats up a lot of code space, so does having to address 16 registers too, in an 8-bit opcode
  • Using an 8-bit accumulator to move data around 16 register of 16 bits each was not a good idea
  • The design makes subroutines and parameter passing very painful

Things improved with the 1804/1805 using opcode 68 as a prefix; unfortunately the ISA was not fully developed.

Interestingly SWEET16 avoids many of the problems since the accumulator is in reality R0. Thus a SEA (Set Accumulator pointer) would have overcome this and also easily lent itself to double width accumulator.

As a bonus, the later extensions also brought in a DBNZ loop branch instruction.


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PostPosted: Wed Jul 18, 2012 9:25 pm 
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Arlet wrote:
I do professional embedded work,
I did that too many years ago now so I am no longer as up to date on the market as I once was.
Quote:
and the niche where 8 bit has sufficient advantage over 32 bit is getting smaller all the time. I used to work with 8 bit CPUs, but now I do everything with ARM (mostly Cortex M0/M3 nowadays). Power is just as low as 8 bit, packages are just as small, prices are lower, and development is easier.
How about licensing costs? ARM makes a pretty penny and I would still expect ARM cores to be more expensive than 6502.
Quote:
I can still see a niche for ASICs running an 8 bit CPU in very high volume, extremely low power productions for a while, though.
Like RFID? I hear plans on RFID on nearly all packaging with tagging and a little logging. That would be an interesting market.


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PostPosted: Thu Jul 19, 2012 4:06 am 
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Alienthe wrote:
How about licensing costs? ARM makes a pretty penny and I would still expect ARM cores to be more expensive than 6502.

Licensing costs could be a problem for ASIC development, which is where 6502 cores (or similar) would have an advantage. If you buy off-the-shelf ARM devices, like I do, the licensing cost would be rolled in the price of the device. In practice, these prices are quite competitive.


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PostPosted: Sun Nov 18, 2012 8:05 pm 
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This is a fun topic and there is no reason to let it go, particularly when I found that 6502 has a virtual sibling in the 65EL02:
http://www.eloraam.com/nonwp/redcpu.php
http://www.eloraam.com/?p=255
Eloraam has extended the architecture with a new stack and autoincrement features and a smattering of other features.

It appears that 6502 was considered by Notch before making his DCPU-16 for the game 0x10c
http://gamegenus.blogspot.com/2012_04_01_archive.html


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PostPosted: Sun Nov 18, 2012 8:46 pm 
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Just the other day i installed the tekkit pack for Minecraft, and there i found the mentioned 6502 emulator, and the forth disk, i quickly connected it all, but i didn't know how to start the contraption. :D Ill give it another try, and maybe convert my server to run the mod.


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