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Before anyone else plans/attempts to build an application for the 6502, at any speed, it would be well to consider the following.
(1) Microprocessors were developed as a means of reducing logic/parts-count in digital electronic products. This was done because the typical all-logic application was from 10 to 1000+ times as fast as needed. Much was accomplished in firmware rather than discrete logic, since the processor, though slow by today's standards, was quite fast enough to accomplish what was needed.
(2) Now that processors are, indeed, MUCH faster, they can do much more in firmware with very simple I/O hardware.
(3) For those cases in which the processor's speed, back in the old days, was insufficient to handle all the I/O related tasks with truly simple hardware, silicon vendors provided large scale integrations (LSI) to handle simple parts of the I/O tasks, e.g. handshaking, interrupt generation, and the like.
(4) Because of the fact in (2), above, some of these LSI devices become more of a hindrance to smooth operation than a help once the operating frequency goes up. For one thing, they can't drive much, that is, they don't have much output source or sink current, hence require external buffering which, if viewed with an eye to (3) in light of (2) could be used without, i.e. in place of, the LSI.
At one time, many of us using the 6502 and other processors, back in the '70's, used software/firmware to generate serial I/O rather than putting in a UART or ACIA. After all, the 6502 was already a precision timer, so a baud-rate generator was superfluous. In fact, so was the ACIA/UART. Don Lancaster published a couple of really decent ways of looking at things microprocessor-oriented in his various video cookbooks. He demonstrated that the 6502 could replace the much more costly 6845 with a bit of firmware, and showed how a display peripheral could be made from a 6502 and little RAM and EPROM.
The problem today is that everyone expects all their devices to be simple to use, like plug-n-play, and they aren't will ing to think over what their real requirements, not ill-conceived desires, but real requirements for a task will be.
The real challenge is in designing a 6502 into your custom gate-array, with whatever functional or instruction-set changes are necessary (not just cute). The 6502 core is implementable in between 2 and 3k gates, which leaves LOTS of room for task-specific peripherals in the remainder of the array, often as large as 250K gates. The 6502 CPU has always been a tremendously efficient (of its own hardware resources) device. It was offered very cheaply at the outset because it was simple and resource thrifty, hence, cheap to produce.
Putting a lot of fancy hardware with it the way the old demo boards did it, doesn't make sense now that the parts are relatively scarce and the processors are too fast to use them when operating at full bandwidth.
. . . just my $.02's worth.
Uli
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