Andrea Griffini's js6502 project on GitHub is a single-page 6502 emulator for the web with a just-in-time compiler.

Just a few hundred lines of code, but doesn't cope with self-modifying code, apparently.

Marvellous.

I was just thinking it should be possible to make a 6502 JIT compiler in hardware Using a 32 bit bus, you can read 4 bytes at a time, and translate each 6502 instruction into an equivalent 32 bit instruction that can be executed in one or two cycles.

I am reminded of the Inmos T9000 (fewer than 9000 sold, quite possibly) which had an instruction grouper: it had knowledge of the capability of the execution pipeline and would group as many operations from the instruction stream as would fit into packets to be sent down. There may be people who still have nightmares about that: there was some kind of grammar as to what the pipeline could do.

More popular was the trace cache in the Pentium 4 - didn't that store microops?

You do need a nice big, and fast, decoder to see what's going on and whether there are any branches or jumps. And some way to deal with half-finished packets, and packets where you arrive in the middle. Oh, what joy! This beast had better be built programmatically.

I don't think you can translate a 6502 instruction into a _single_ 32bit instruction and execute it in one (or two) cycles. The reason for this is the address calculation involving address reads and index computations. You could probably translate a single 6502 instruction into multiple 32bit instructions executable in one cycle each.

André

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Yeah, you're right. Indirect zero page addressing, for example, would be quite hard to translate. Maybe not impossible if you're willing to cache memory contents in local registers, but that's going to be a beast to implement.