Hallo allemaal,

I started to revise my TTL6502 project, http://www.baltissen.org/newhtm/ttl6502.htm, and was thinking about to expand it a bit. One idea was having 16 bits registers. The idea looked good for weeks until the thought struck that my 8-bits ALU couldn't handle these registers
My momentary ALU is made of two cascaded FlashRAMs, each handling 4 bits of the two operands and a total access time of 140 ns. I could emulate a 3 MHz 6502. To be able to handle 16 bits I need to cascade four FRs, meaning 280 ns. and thus 1 Mhz max
Why FRs? Simple answer: the most quick and dirty method. I have thought about using 74181's but the decimal mode spoiled the fun.

Has anybody an other idea to realise the ALU?
Many thanks in advance!

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Not sure about the 16-bit case, but for the 8-bit case a couple of half-baked ideas spring to mind
- use a carry-select approach for the upper nibble, so you have 3 rams but only a little over a single ram delay in the critical path.
- apply a decimal adjust like the 6502 does, so you cascade two 181s for each nibble, one for binary and one for the decimal adjust. You still get a ripple delay for each nibble, but at 181 speed instead of 29f040 speed.

Do either of those ideas work?

Ruud:

I had looked at your website several months ago, and was certainly impressed by the dedication and the perserverance needed to built your CPU. Tip of the hat to you.

On the subject of your question, I will suggest considering an implementation based on a bit serial, or a nibble serial implementation. This is the next approach that I will take on my FPGA-based 65C02 core, but it is something that you can also use in your implementation. You may have to run the ALU section at a sufficiently higher frequency in order to maintain a reasonable overall performance.

If you implemented the ALU as a nibble mode, the '181 ALU and '174 D-register on the ALU output and '74 D-FF on the nibble carry out should be sufficient to perform the sums and other operations. Furthermore, since the basic ALU operation is nibble wide, it may work to your advantage in the implementation of the BCD mode for the ADC/SBC instructions.

Also, you would have several different ways to multiplex the appropriate sections onto the ALU inputs. For example, octal registers followed by '240/'241 dual 4-bit tri-state drivers, or any number of other combinations of registers, tri-state buffers, and multiplexers. I daresay that you should be able to operate your core at a high enough frequency to achieve a respectable instruction execution rate.

I suspect that 12-16 MHz should be something you could achieve as long as you don't use TTL parts with extremely fast edge rates, i.e. do not use FCT, BCT, or similar logic families. You may have to use series damping resistors in the ALU section, but I doubt that they would be necessary for the rest of the CPU.

Didn't this topic have more posts?

Anyway did you try to make the alu just from logic ic, once i used the espresso algorithm which can track common segments in various output functions, and by doing so, it minimizes the logic ic count.

There's a doppelgänger thread. It confused me too.
Cheers
Ed