teamtempest wrote:
...Oh my gosh that's a lot of opcodes! Way too many to put into a built-in assembler mnemonic table. Space is one reason; trying to make certain they all get entered correctly is another...I took a brief look at your macros. I see you've pretty much decided to indicate address mode in the name of the mnemonic itself. Practical but
maybe not in the true 6502 spirit ..
I've tried to be true to the core of the NMOS6502. I'll have to do a full writeup on the workings of all the opcodes very soon! As in tomorrow, because you are interested!
But, some clues
here as to my ramblings.
So tired, sorry. Will summarize tomorrow... But I've got decent comments on the opcodes on Github...
To start, all the 255 other pages of the opcode matrix follow the
original matrix layer $00. BTW, there is
some room for mobility as far as defining opcodes with the same src/dst_reg's. Right now, INC [A..Q] differs from INY, INX, INW, i.e. accumulators with same source/destination reg's are different than index registers with the same source/destination reg's, but they can be made to have the same upper 8bit structure, if this helps. What I mean is, I can change
some values in order to help the assembler program...
teamtempest wrote:
...On another note, I'm not sure I understand some of the macros. Are there some ADC and SBC variants that take three operands? They have very long names and it appears as if source register, destination register and immediate value are all specified. Is that correct, or am I misreading them?
The ADC/SBC are
some of the logic (52?) functions I previously mentioned, where the source and destination reg's are defined by the upper 8 bits of the opcode,
per addressing mode. 4 bits for source, 4 bits for destination. So just 1 ADC (zp,x) for example can have 256 opcode variants alone, since it has 16 possible source accumulators and another 16 possible destination registers. The operand part of the sequence is the same as the original 65Org16. On the whole, this core is transparent to the original 65Org16! except for the D flag/opcodes. Notice where I have INW and DEW...
EDIT: Sorry I had to delete and repost this entire response. I had attached a .b core spec sheet. But I realized there is a glaring mistake in the code where I was attempting to do an accumulator transpositional store on the 16 <shift,rotate> opcodes that work on memory locations. I will attach the spec sheet again, but I thought I should delete it so as not to waste server space with erroneous information.