Hi there,

I am looking for a home for my 65k processor core. I am looking into continuing my "Gecko" line of single-board computers with a FPGA-based Gecko65k. The current draft for a gecko65k design see attachment (trying out this feature of the new forum software

- based on OHO GODIL with Spartan 3E with 500k gates
- 1Mx8 / 512kx16 RAM
- 512kx8 ROM
- USB host, device, Ethernet, SD-Card via SPI
- can be processor card for my CS/A65 computer

and finally:

- can plug into a 6502 socket to replace the CPU of a 6502 computer!

What do you think?

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Your past work has been very impressive, to say the least-- but this is awfully hard to read.

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What's an additional VIA among friends, anyhow?

I'm sorry for the bad quality. This is one of the sketches I do before going into the eagle drawing tool. The previous times I have published it mostly when I had an already working version - for this one I wanted to get some earlier feedback... I have attached a new (hopefully better readable) version.

Here is some further explanation:

On top there is the GODIL - a Spartan3E package with 50 I/O pins in standard 2.54mm distance pin rows, so it's convenient to use (not SMD that is) Below that are different functional groups. Roughly: to the right is the 6502 and CS/A65 connector feature, in the middle the RAM and ROM, and to the left the SPI interface.

I have defined a single address bus with 19 address lines (A0-18), for up to 512k addresses. Those are connected to the two RAM and single ROM chip. Then I have D0-7, the main data bus. It is connected to the ROM and one (not both!) of the RAM chips. The second RAM chip uses the "AUX" bus as data bus. This bus is used twice - as "high byte" for a 16 bit RAM (512k words of 16 bit as combination of the two RAM chips), and as an I/O interface bus.

As an I/O interface bus three signals are used as simple video output (HSYNC, VSYNC and VIDEO) - you could for example connect a Commodore PET monitor (given the correct timing). The other five bits are used to implement a simple SPI interface. They provide MOSI, MISO, CLK, and two address selects for four devices. The 74x139 and 74x153 then decode the select signal resp. select the correct MISO signal for the device to be used. The /AUXEN signal enables the I/O functionality, so you can switch between I/O and RAM usage.

There are four SPI devices planned: USB Host, USB Device, Ethernet and an SD-Card interface. All of them require 3.3V, so there are level shifters (74LVC4245) in between.

The RAM should be accessed at high speed, so the "slow bus", that is connected to the 6502 and CS/A65 connector is separated by 74x245 data bus drivers and 74x273 address bus drivers. The latter because they have a CLR signal, so I can easily switch to "reading address zero" when the CPU is actually doing lots of stuff on the fast bus. This avoids accidentally triggering any read triggers on any I/O chip on the slow bus. /CON65 enables access to the slow bus. /CONIO determines for the CS/A65 connector, if I/O or memory area is selected.

With this setup I use all the 50 I/O pins of the GODIL, so I hope that it actually works as planned, as there is no pin reserve. USB host and device interface provide sufficient extensibility, Ethernet for connectivity, and an SD-Card as external, exchangeable memory storage.

So what do you think?

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Hi, Andre

Wow, it's quite a recipe you're cooking up. I can see you're planning to really have some fun! I'm envious!

Regarding the level shifters on the left of the diagram, it seems to me you could eliminate the 3.3 -> 5V unit by feeding the 3.3V logic signals directly into 74HCT series devices -- ie: 74HCT153, 74HCT08. This family of devices are CMOS and use a 5V supply but their inputs accept TTL levels. I expect your 3.3V signals will have rail-to-rail voltage swings, meaning that logic high will be the full 3.3 volts. In TTL terms 3.3V is acceptable as a High, so you'll be OK. (I just looked at a 74HCT08 data sheet; that chip accepts 2.0V or greater as being a High.) Another option is the 74ACT series (which is faster than 74HCT); I think there are other, even faster CMOS families that also accept TTL levels on the inputs.

It looks to me as if there's a bug in the AUX bus logic. AUX is a bi-directional bus, but the enable for the '125 tri-state buffer that feeds MISO onto AUX7 doesn't seem to be qualified with regard to R/W. There's a chance the '125 will sometimes drive AUX7 at the same time the GODIL is also driving that line. Does that make sense -- do you see what I'm talking about?

What goes on the CS/A65 connector? Also I'm curious why it gets separate MEMSEL and IOSEL signals.

Cheers,

Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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Thanks for the comments!

Yes, it seems I'm always heading for the interesting - or more complicated... - stuff...

Yes, I could replace the 3.3->5V level shifters with 74HCT logic, that's true, I've done that before. This is only the first concept and the level shifters in this diagram are kind of placeholders until I do a real schematics. Also The glue logic may be consolidated into a small CPLD for example (or rewritten to reduce chip count).

ABout the AUX bus, good observation. The AUX bus will be used as 7 bit output and 1 bit input when /AUXEN is active, and as D8-15 when /RAMHI is active. The GODIL just has to make sure not both are active at the same time.

The CS/A65 bus connector is basically a 6502 bus with additional lines. I used in (for more than 20 years now actually) in my line of self-built computers. Please see http://www.6502.org/users/andre/csa/index.html for more details. The idea is to be able to reuse the boards there (e.g. to use the Gecko65k as processor card for a roll-your-own PET replica I can build with this system). The bus has two lines, /MEMSEL and /IOSEL to address two address spaces, one for memory (1M addresses) or I/O (4k addresses).

André

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Or 74ABT series. ABT silicon has single digit prop delays.

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