I tried to investigate the implementation. The
project is described in
ABEL HDL (pdf), which needs an older version of the Xilinx tools: perhaps version 10 is the latest which will support it. I had some success using 8.2 command-line tools (with cribs from
here) to convert to user-unfriendly vhdl and then synthesising in version 11. It still failed to fit a XC95108-7-PC84 with default tactics or even with adjusted tactics:
Code:
Mapping a total of 108 equations into 6 function blocks....................................ERROR:Cpld:892 - Cannot place signal VSI. Consider reducing the collapsing input
limit or the product term limit to prevent the fitter from creating high
input and/or high product term functions.
Attempting to reduce the input or product term limits seem to lead to an impasse with:
Code:
ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least
109 but only 108 left after allocating other resources.
So this design does seem to be right on the limit, if not a little over.
Probably re-writing the ABEL in a modern HDL and studying the implementation would be the thing to do, if it is worth pursuing - or using the supplied JEDEC files if it is good enough as is, which means targeting the exact device.
Cheers
Ed