Does anybody have any information/experience with the actual (as opposed to datasheet) Write Data Setup Time on the NMOS 6502?

I know that MOS specify that valid Write Data is ready no later than 200ns after Phi2 rises (and Rockwell and Synertek say 175ns for the same).

I also know that the specified Read Data Hold times (100ns prior to Phi2 falling) is somewhat over-exaggerated and that at least several 6502 computers couldn't work if this was the case (the Apple II springs to mind), so I was wondering if the same was true for the Write Data Setup timing (especially considering MOS' early checking-out methodology....).

Does anybody have any real-world experience/information as to how soon valid Write Data is available in practice on NMOS 6502s?

The only way I can think of to get that info is to experiment, possibly feeding it the clock input signal from a pulse generator with the high and low times individually variable, and using an oscilloscope to watch the data-arrival times compared to the φ2 edges to see how much time works before you get the pulse width narrow enough to make it crash.

It kind of sounds like you're thinking of building something new with it though; and in that case you might as well use the CMOS 6502.  The only disadvantage is that it won't run the NMOS's illegal op codes.  You get more instructions though, more op codes, bugs and quirks are gone, much higher speeds, much better bus-driving strength, much lower power, it's being made today, etc., etc..

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Not really something new, per se: specifically, this particular project is a personal challenge: could I build a state-of-the-art, feature-packed microcomputer for production... in late 1975? Yes, if I were creating a new system, I would use the 65C02; but in 1975, of course, there's only NMOS (and yes, I'm making sure that my code doesn't contain any RORs )

I'm currently reworking the DRAM strobe timings (MK4096-16) on my prototype, and was wondering if I could get away with using an early write cycle instead of a delayed write strobe, which makes signal generation a little easier (with consequent reduced chipcount).

As far as I can tell with my oscilloscope, both the (Rockwell) 1MHz 6502s I've looked at seem to always have valid data by Phi2+120ns (and probably earlier than that, possibly consistently as early as Phi2+80ns), no matter which instructions I throw at them. However, I have no idea how representative that is (i.e. should I rely on that if I were designing for production?).

Specific concern aside, of course now I'm also just curious and would like to know regardless