Ok, not too difficult. Only one opcode, $F2, unaccounted for. But this is a 65C02 instruction! Old habit, I am looking at the WDC datasheet for the opcode matrix...
Next in true hacker fashion (i.e. one who is just learning), I look for where else these opcodes occur after the state machine. I find a piece of code for load_reg and modify bits [11:10] for the matching opcodes (not shown).
Modified Microcode State Machine. Bits 11 & 10 will point to a dst_reg. The src_reg will also read these bits.
Code:
DECODE :
casex ( IR[15:0] ) // decode all 16 bits
16'b0000_0000_0000_0000: state <= BRK0;
16'b0000_0000_0010_0000: state <= JSR0;
16'b0000_0000_0010_1100: state <= ABS0; // BIT abs
16'b0000_0000_0100_0000: state <= RTI0; //
16'b0000_0000_0100_1100: state <= JMP0;
16'b0000_0000_0110_0000: state <= RTS0;
16'b0000_0000_0110_1100: state <= JMPI0;
16'b0000_00xx_0x00_1000: state <= PUSH0;
16'b0000_00xx_0x10_1000: state <= PULL0;
16'b0000_00xx_0xx1_1000: state <= REG; // CLC, SEC, CLI, SEI
16'b0000_0000_1xx0_00x0: state <= FETCH; // IMM
16'b0000_0000_1xx0_1100: state <= ABS0; // X/Y abs
16'b0000_00xx_1xxx_1000: state <= REG; // DEY, TYA, ...
16'b0000_xxxx_xxx0_0001: state <= INDX0;
16'b0000_xxxx_xxx0_01xx: state <= ZP0;
16'b0000_xxxx_xxx0_1001: state <= FETCH; // IMM
16'b0000_xxxx_xxx0_1101: state <= ABS0; // even D column
16'b0000_00xx_xxx0_1110: state <= ABS0; // even E column
16'b0000_0000_xxx1_0000: state <= BRA0; // odd 0 column
16'b0000_xxxx_xxx1_0001: state <= INDY0; // odd 1 column
16'b0000_xxxx_xxx1_01xx: state <= ZPX0; // odd 4,5,6,7 columns
16'b0000_xxxx_xxx1_1001: state <= ABSX0; // odd 9 column
16'b0000_xxxx_xxx1_11xx: state <= ABSX0; // odd C, D, E, F columns
16'b0000_00xx_xxxx_1010: state <= REG; // <shift> A, TXA, ... NOP
16'b0000_00xx_10xx_1011: state <= REG; // TBA,TCA,TDA,TAB,TCB,TDB,TAC,TBC,TDC,TAD,TBD,TCD
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