This thread is intended for discussion of 'sandbox' ideas - things that may not be practical, but would be interesting to consider, at least.

Here's a couple of ideas:

Build a dual-processor system where the 2 CPUs share a portion of memory (use "2-port memory").

Perhaps one of the CPUs is a 65C02 running at 14 Mhz, while the other runs at a slow speed. The fast one has access *only* to the 2-port RAM, and maybe to a fast I/O device (if any). The slow one has the ROM, the UART, and other 'slow' I/O devices. When the slow one boots, it writes *code* into the 2-port RAM - this code is what the fast one boots from. So, the fast one becomes a high-speed 'engine' that is controlled by the slow one. I.e., the fast one does complicated floating-point math or something...

Is there a way to implement anything like 'pipelining'? Or any sort of 'pre-fetch'? I suppose not, without getting into the guts of the CPU itself...

What about putting a hardware 'wrapper' around a 6502 system, so that it works *serially*, like the PIC chips do. That is, actually execute code over an RS-232 line. It should be very do-able, but is it useful?? With a "serial CPU", we could use our PCs as the "memory" - like having a 6502 system with multi-gigabytes of "RAM" and "ROM" - we could ignore the 64K address space limitation.

Pete

Your idea of running two CPUs that share memory and I/O is a neat one, it reminded me of a technique that was used in the old Commodore PET/CBM drives. Two 6502 CPUs, running on opposite sides of the phi0 clock. Not quite as sophisticated as your idea, but quite neat in itself. There are some schematics for the old drives on ftp.funet.fi somewhere inside /pub/cbm if you want to check out how it was done.

_________________
- Mike Naberezny (mike@naberezny.com) http://6502.org

Heh this is what I was suggesting earlier in a previous post:
Interface the 6502 with a microcontroller that has
the peripherals you want. I was actually thinking of
a DPRAM, which I've used a number of times. They are
really neat.

The way I figure, with three chips, (6502, DPRAM, and

the microcontroller) you'ld get
1) a 6502 'engine' (to use your words)
2) serial port, I/O, A/D, timer from the microcontroller
that can be configured/used by the 6502 through the dpram
3) programmability of the microcontroller using an ISP
interface (here I'm thinking of the Atmel microcontrollers)
4) programmability of the 6502 through the microcontroller
over the serial port, writing to the dpram.

Advantages:
1) smaller chip count.

2) in-site programmability
3) more available parts.

Disadvantages
1) DPRAMs arent cheap
2) added complexity of programming the microcontroller
3) synchronization issues

For an even more off-the-wall idea, I figured the
best way to do away with all the disadvantages

altogether is to write a 6502 emulator on the microcontroller
itself This has led me to more philosophical musings
about why I love the 6502. It certainly isnt the

pin count, packaging, or anything related to the hardware.
Besides reasons of nostalgia (I grew up with a ][+), its
the fun instruction set, the 'software' if oyu will.

If anyone here has written an emulator (The best
I've done is to write a 6502 assembler) I'ld appreciate
any comments on viability and speed.

Robert

I have designed a 6502 coprocessor board for my selfbuilt 6502 computer.
It uses time-shared RAM, so you don't need dual ported RAM.
It has synchronization stuff in place, and the master CPU can reset and
stop the slave processor. The slave processor also has an I/O bus to

connect to SCSI, or Serial line. The intent was to have a second processor
doing the heavy stuff like SCSI interfacing or TCP/SLIP code.

See http://www.6502.org/users/andre under CS/A65

Andre

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

In th mid to late '80's Rockwell ran adds and published data sheets for a controller chip that had two 6502 processors on the chip. They ran on opposite phases of the clock. I tried to get samples for a couple years, but they apparently never made any.

In the "design project" thread, Mike mentioned that he might make up a batch of boards to be used as 'trainers'.
How about building a board with a bunch of LEDs on it to show the state of address, data, and control lines. Then, run the clock at a very slow rate (like 1Hz or less).
A similar thing could be done with a fast clock, if you add logic to do single-stepping; *but*, I'm thinking that you would lose visibility to some signals that way (true??).
It would be cool to build a 'graphical display panel', with the LEDs behind it, lighting up various signal paths on the diagram as they happen...

So, is a 65C02 'fully static', so that you can run it at very slow speeds, or stop it indefinitely? As I recall, the old NMOS version does not allow this (?).

Pete

Hello,

<<< Begin quote

So, is a 65C02 'fully static', so that you can run it at very slow speeds, or stop it indefinitely? As I recall, the old NMOS
version does not allow this (?).

End of quote >>>

The reason why you can't run an NMOS 6502 at such a slow speed is that tbe way NMOS works, you have minimum and maximum rise and fall times. The chip will NOT function properly (probably not at all) if you slow it down that much, because the clock pulses will be too slow to be registered as pulses by the circuitry. Now I'm not an EE just yet, but I'm pretty positive on that statement.

Regards,

Tennessee Carmel-Veilleux
veilleux@ameth.org

Some of the S-100 Bus Computers Had "Front Panels" that had LED' s and swithches for the Address & Data buses. You could also single step the cpu from the Front Panel. I've got a board for the S-100 Bus that just has the LED's at the top of the board. This board is extended taller than a standard board so that you can see the LED's. It's a neat display.

The 65C02 is a static design. It even has a "STOP" instruction. The 65C134 microcontroller is based on the 65C02 core. It has two clocks. A "Slow" clock of 32KHZ and a "Fast" clock of up 14MHZ. You can switch between the two. It's mainly for battery operation to save power on the "Slow" clock.

The NMOS 6502 was a dynamic (like dynamic RAM) and required a minimum clock rate of 100 KHZ for the 1 MHZ parts.
Ted

In another thread, Brian mentioned speech-synthesis using large ROM lookup tables and such.

One feature on my 'list of things to do' with my current robot project is to add phoneme-style speech synthesis in Japanese.

The reason I want to do Japanese is:
- My wife and daughters speak it (much better than me!).
- Japanese has only about 65 basic sounds in the whole language, and those sounds are fairly 'discrete' - just string the sounds together in the right order, and you should have 'understandable' speech.
- There is a standard for Romanized spelling of Japanese, and there are very few exceptions. So, it's easy to write software that does text-to-speech correctly (it's a nightmare in English).

The plan is to have my wife record the 65 sounds into my PC's sound card as a WAV file, then I blast the data into Flash on my 6502 board, and it uses a D-A to play it back. I'm figuring that about 64K will be needed for 8-bit samples.

Pete

Hi, Pete

Just saw your post about playing back 8-bit .WAV files through the D-to-A -- sounds like a very cool application!

If you haven't done a lot of work with sound processing before, feel free to ask me anything you want (I do this day in, day out since I work in the electronic toys industry!). You can either post here, or E-mail me directly at Brian@STMProducts.com and I will reply within a couple days.

The biggest trick after getting a clean recording and choosing an appropriate sample rate (I usually use 6KHz for voice, 8-10KHz for music instruments and sound effects by the way) is dynamic range compression. Most software packages like GOLDWAVE, SOUND FORGE, etc will have user-definable DRC or "distortion". As long as you compress down the attacks in the hard consonant sounds you can then expand the finer details in the rest of the sample. This makes the little sounds "brighter" and much more perceptible to the human ear, giving much better listenability.

-- Brian

Thanks for the hints Brian!
I'm probably at least a couple of months away from doing anything with voice-synth idea.

Pete

Here's another idea, from the discussions on slow vs fast devices and such:

Build some logic to change the input clock speed on-the-fly, based on which block of memory was being selected.
For example, run the CPU at a fast speed like 10 Mhz, but use 1 Mhz 6522's on the same bus. When the "slow memory" area is selected on any given cycle, then s-t-r-e-t-c-h the phase 1 and phase 2 times by a factor of 10. Maybe use a decade counter (div by 10) to control things, so that you would always get exactly 1/10 of the normal speed on that particular cycle.

The RDY signal allows for stretching a Read cycle, but it doesn't work on Write cycles.

Anyone already done this?
Any commercial products do things like this?

Pete

The Apple IIgs changed clock speeds depending on the area of memory and such. They had the processor going at 2.8 MHz, but they still needed to have some areas of the machine to have a 1MHz clock to match the Apple II design.

And you could change the clock speed from 2.8 MHz to 1 MHz from the control panel.

>The RDY signal allows for stretching a Read cycle, but it >doesn't work on Write cycles.

The RDY signal allows stretching a Write cycle also on a 65C02. I would suggest using this CMOS variant chip wherever possible.

>Anyone already done this?

I've seen an old article in Nov 83 issue of Elektor India which did exactly this. The circuit - "CPU gearbox" switched to lower clocks whenever the CPU was accessing I/O devices.

This is an excellent idea for experimenting.

Another idea that I have tried is:
The 65C02 is a fully static device and can work at upto 0 Hz clock. The clock can be held infinitely in the high state. In my CPU board , I have built a provision to adapt the system clock with an external circuit to control the CPU clock-by-clock or at a variable clock.A simple counter counts the clock pulses.It is an extremely educative circuit for analysing signals at any state.The "Clock control Circuit" is connected externally via 8 header pins(a jumper is put across two pins during normal operation).If such a circuit is microcontroller controlled and can read the system bus,one can build a useful circuit to freeze the CPU based on the state of the system bus such as during interrupts, when a critical code is being executed etc.

Did you guys see the announcement of the new "Crusoe" chip?
It sounds like one of it's features is that it slows down it's clock whenever the system is not busy (such as when waiting for the user to click the mouse, etc.). Since power consumption is closely related to clock speed, they can get 4X better battery life on a laptop, but still run at 700 Mhz when necessary.
I guess the speed control comes from software - they talked about a translator program for existing EXE images.

Pete