See the discussion at viewtopic.php?t=195 which adresses this exact thing.

Thanks, if i got it right, there might be issues interfacing hc and ls, and cmos inputs take longer to charge?

The main interface issue is the voltage levels, which is what 74HCT was made to remedy-- to get the benefits of CMOS while matching the voltage levels to TTL and LS. LS still has input capacitance that must be charged up, but the DC loading at LS inputs becomes rather major, unlike the situation with CMOS. CMOS has an infinite fan-out at low clock speeds (ie, an infinite number of CMOS inputs can be driven by a single output), whereas LS is still limited to 10-20 even at zero Hz, and consumes power even at zero Hz.

There have been times that I needed a 74HC IC that I didn't have and didn't want to wait for an order to arrive, so I got the LS version at a local store and plugged it in and mated it with HC parts in the same circuit, and it worked. It's not really guaranteed to, but so far it always has for me. The main issue would be that LS can't pull up as high for a logic 1 as HC outputs can and as high as HC inputs expect. HC outputs can pull up almost all the way to 5V with HC loads, but LS outputs theoretically may not pull up quite far enough for an HC input to recognize it as a valid logic 1.

Can i then use exclusively ls(with few exceptions) in my sbc, will other nmos(or hmos in the 68000 case) ic, or other(ram,rom...) complain? Until now i had 4000 glue logic, and 74ls139 decoders, and it worked fine, but i now decided to use 74(at the local store i found ls) for better performances.

Edit: Sbc-2 uses LS(as seen from the pictures), but Sbc-2 uses cmos versions of the nmos chips.

Can the 4053 be used for switching from color to black and white mode, this is kinda useful, since the chip does not have white in its color palette.
And can the 4053 be also used for switching the css and inv from a static state, to the two extra bits from the crtc ram?
Or is there a 74xx solution(if the 4053 can't handle this)?

There's the 74HC4053 which is almost 20 times as fast as the 4053 at 5V. I thought it would be hard to find, but I see Mouser has lots in stock in lots of versions, including DIP, at http://www.mouser.com/Search/Refine.asp ... d=74HC4053 , and the price is reasonable.

Any hope that the 4053 could work?

I haven't seen your timing requirements; but again 4000-series stuff is really, really slow. When they say 1MHz, that definitely does not mean it's suitable for use in glue logic for a 1MHz computer. It's more like, "This can toggle at that rate and hit the rails briefly," or "This counter can count at that rate."

I intended to use the 4053 only as a analog switch for bypassing the signal from the chroma modulator, so i can get black and white graphic. And if it is possible to switch data signals like described on my previous post. The operation would be static, only the switched signal would change.

It is a miracle, I've found the 74hc4053 at my local store, but the seller said that there are only few left, and that this is a very rare ic, and i had to pay it 34kn(6$)...

So from my data book, it looks like it should work then. There's very little difference in the performance when not switching. The HC has less distortion, but they're both very low.

Finally i got some free time, and i went to finis the graphic module, so i managed to solder the basic parts, but now i have some trouble when i try to write data into the video ram. When i try to poke a location in the video ram, i just get artifacts on the screen, but no change in the ram, but when i grounded all the address inputs, then when i poke again, i got the poked character at the top left corner of the screen(location 0 in ram). The address bus is interfaced by two 74hc573, and the data bus by one 74ls342. The latches are controlled by the MS output form the glue logic shown in the picture.

*All 4000 logic has been replaced by 74ls
*S is set to fast
Any ideas?

I don't see any obviously wrong thing here.

One point though: Obviously you gate /WE with Phi2 - but it takes three gate delays from phi2 to /WE - I'd rather try to gate /WE with Phi2 much closer to the output. For example instead of U4A use a NAND gate with Phi2 on one side and the correct combination of /CS, /FS and S on the other side. So the clock delay is minimized.

You don't show what drives the control signals of your data and address buffers. So I can't see if there might be any bus conflicts during the time when the CPU accesses the memory and when the video accesses the memory. Also how is the RAM /CS and /WE controlled? Are the VDG and processor clocks synchronized?

From the symptoms the snow on memory access seems logical - similar to the old Commodore PET video memory access. When the CPU writes to the memory, the video logic can not read the correct value, thus displays garbage.

Seeing that you get the correct data value in when you ground all address pins, it looks like there could be an address conflict between the VDG and the CPU address lines. The CPU and VDG address lines mangle and the memory is not addressed correctly. So you need to check the control lines for your data and address buffers

André

The device is quite simple really.
The MS signal is directly tied to the OE inputs from the data and address latches(the latch input is always set, so the latches are transparent) and to the crtc ms input pin, the data buffer direction is tided to r/w through a not gate. I only have 3 ic sockets for the glue logic, i don't have any other free space left. I also have 2 latches which only act as settings registers, for switching the crtc settings bits, also for switching from color to black and white(by bypassing the color modulator with a analog switch), and for switching between 4 video ram banks(i use a 32k ram, but only 8k is addressable, this feature is nice if i am going to make some kind of menu, or similar stuff, so i won't have to rewrite the entire video ram). The clocks are not synced, as for the snow, i use the S input, which will enable writing in the video ram only when it is not accessed, if it is accessed when the crtc chip is reading the video ram, the rdy output is asserted.
I didn't connect any of the settings latches yet, so you can ignore them(the setting are now tied to high or low).

Note: I am not currently in Zagreb(the semester ended), i went home this week, and i left all my stuff there.

I've looked over your logic and it should work. I assume the CS signal is dervied by decoding the CPU address bus.

The snow on the screen when you write to the screen indicates that something is happenning.

Since it works with an address of 0 but not other addresses, the most likely problem is that you are writing to an area of memory that isn't shown on-screen. Check that the buffered CPU address lines connect to the corrosponding VDG address lines.

One thing that might be worth trying is a brief test program that pokes every diaplay memory location with the high byte of that location's address. This should cause something to appear on the screen and from the characters that appear you can identify where in the memory the VDG is displaying. If nothing appears, there is obviously a problem with your logic. Either MS is not being driven amd the VDG and CPU addresses are conflicting or you have a problem with the write pulse.

_________________
Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!