BigEd wrote:
Hi EEYe
What do mean by verilog being preferred language? I don't think Xilinx prefer anything - they support everything, because they just want to sell lots of FPGAs...
By preferred, I meant what is chosen at the beginning of a project...
BigEd wrote:
...Verilog/VHDL is a long-running question which people can get quite heated about - usually people have a strong preference...
I've been reading abit more and not too much is mentioned in Xilinx forums, except that a separate license is required and third party software like Synopsys or Mentor is needed to generate the .sv file, so most likely Xilinx XST will not be supporting systemverilog anytime soon.