Elsewhere, Garth rubbed a lamp and wished for a 3,3V module with 0.1inch pitch connectors, to provide a 65Org16 CPU in a pre-programmed FPGA:
GARTHWILSON wrote:
... as everything else becomes available in 3.3V, that will be fine.
Quote:
The smallest FPGA that can fit a 6502/65Org16 core are in 100-pin packages, so you would need some sort of 100 to 40-pin adapter for A 6502 core. And a larger adapter for the 16-bit version. At least 32 pins for address, 16 pins for data bus...
If someone could supply them on an optional adapter board with pins to plug into hobby-friendly dual- or triple-row sockets, that'd be great.
![Image](http://www.samtec.com/ProductInformation/TechnicalSpecifications/images/SSQ.GIF)
(The picture on the left is about twice actual size and only shows 10 positions, but the socket strips are available in much longer strips that can be cut to the needed size. I know there are WW ones too, but I can't find a picture of one right now.)
I envision the layout being something like:
Code:
x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x
x x x x x x x x x x x x x x
x x x x x x x x x x
x x x x x x OR x x x x
x x x x x x x x x x
x x x x x x x x x x
x x x x x x x x x x x x x x
x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x
on .100" centers. I don't think anyone expects this to go onto a 40-pin DIP equivalent package.
So I would hope the the FPGA gurus would make these special processors available to all who want to order them, and that the HDL be public domain so if one person doesn't feel like continuing the project, others are not orphaned.
Following on from that, we noted that the HDL is already public domain, and that non-volatile FPGAs do exist, so the board doesn't need too much on it. (Also we had a plea for a 40pin footprint in addition, and a preference for dual row connectors. I think four dual rows might be best, with spacing to allow a subset to serve as a DIL footprint. The dual rows would be half signal, half shield.)
I then realised that such a thing is called an FPGA breakout board. They exist, priced from $50 up. (It still might be worth designing one for our purposes and making a batch, or thinking of it as a business because existing breakout boards just don't have the right feature set.)
Here's an example. It's a two-part board - the left part has not quite enough and the right part adds a bit too much:
See also
Pluto boards
Here are two more with around 50 I/Os, both of which have open source licenses, so could be a basis for a redesign:
Edit: updated title