I just looked at a Rockwell NMOS 6502 data sheet, and the maximum Clock Cycle Time is listed as 10 uS -- ie, 100 kHz is the slowest they guarantee that the chip can go. (The same figure applies for their 1 Mhz and 2 Mhz versions.) So, for you to operate thousands of times slower than that does not sound reliable!

A related point is that you need decoupling capacitors physically close to your circuit, just the same as if it were a logic IC.

Also, a reminder: remember that the ground on your oscilloscope probe needs to connect physically close to your circuit. This is a basic -- but crucial! -- issue. When observing any high-speed circuit the 'scope display is sure to be a mess unless you have a proper ground connection at the end of the probe.

With proper construction this circuit should work fine. But the collector resistor needs to be fairly small (2K, 1K or even less). The capacitor in parallel with the base resistor (as Garth suggested) is a good idea, too. Let us know if you have a chance to 'scope the circuit again, incorporating the changes.

-- Jeff

I was hoping to be able to get the 6502 working in almost static condition for debugging...

At least that is fairly easy since you can run a super slow to static clock on the 65C02.

_________________
"My biggest dream in life? Building black plywood Habitrails"

Can you rig up a single-step circuit using RDY input and SYNC output?

(Several circuits offered linked from that search, but here is Woz' design from the Apple 1 on the right:

)

Jeff, the speed thing does NOt relate to the 65C02 which can go station. A 10 hour per clock cycle is perfectly feasible on a 65C02 while not possible on the older NMOS version....

_________________
"My biggest dream in life? Building black plywood Habitrails"

What exactly happens on a 10hz clock, when i tested it worked, but what happens after a while?

If it seemed to work at 10Hz when they specify 100kHz minimum, that's quite a "safety margin," but what I had read decades ago was that the NMOS one had some registers that were kind of like DRAM which would hold its state only a short time before needing to be refreshed. I guess it wasn't a problem because at normal running speeds it didn't just get refreshed, but got new data stored with every instruction, so it would never lose its charge. In the CMOS one, they were replaced with flip-flops which work more like SRAM. So you take the clock speed down too low on NMOS, it won't hurt anything, but it won't work either. Before the W65C02S ("S" meaning "static") that came out about 20 years ago IIRC (or maybe it was the "B" that came out at that time-- I can't remember), 65C02's could be stopped only with phase 2 high, which I've done several times, but with the S version, could be stopped in either phase.

If you want to halt the cpu, why can't you just connect the phase 1 to the rdy, why the need for all toes circuits?

That's true, and worth remembering. But Dajgoro specifically mentioned the NMOS chip.

You're right -- it is easy to halt the CPU. But remember you also want a push-button circuit capable of un-halting for a single cycle and then automatically halting again, so really the challenge is less simple than it seems.

There's quite a fancy circuit in the MOS MCS6500 Family Hardware Manual on page 125 (Figure 3.1). It's fairly complex but it offers the ability to step one cycle at a time or one entire instruction at a time.

If you don't need the instruction-step feature, you could probably create a much simpler circuit of your own with just a flip-flop or two and a debounced pushbutton signal. BTW the NMOS 6502 ignores the RDY pin during all write cycles, so you can't single-step those.

It's worth reading Chapter 3 of the manual I mentioned. In fact, the entire book, and its companion publication, the MOS MCS6500 Family Programming Manual, are excellent.

-- Jeff

Today at the break between two classes of math, i went to the electronic store behind the faculty, and i bought two BFR90 5GHz transistors (previously i used the BC109C 150MHz). I think they might fix my single transistor inverter problem, i hope it works...(Will it work?)

The speed of the transistors is not the issue so much as the RC time constants in this kind of circuit. A fast transistor will be able to jerk the output line to the rail in a hurry; but when it turns off and the pull-up resistor is left to float the line back up, it will take its time charging up the stray capacitance on the inputs of the next logic stages, the PCB itself, and the sockets. I worked in applications engineering in the mid-1980's though in VHF and UHF power transistors, and I can tell you that they do not behave the way you would expect. At hundreds of MHz the input impedance becomes very low and even the bond wire inductance is a big deal.

The capacitances of the BFR90 are much much smaller than toes from the BC109C. The distance from the transistor to the resistor should not exceed 1cm, and there are no relative neighbours wires. Where else do capacitances occur?
It seems that i should be making another visit to the faculty's lab...

Much of the capacitance I'm thinking of is the load connected to your output.

Yes... I forgot to mention that... The input capacitance for the latch is 3.5pF, BC109C collector capacitance is 6pF, for the BFR90 is nearly 0.5pF.

I replaced the BC109C with the BFR90, and i changed the resistor values, and it works fine at 1MHz...
But i have another mystery... The other day i got my new 20x4 blue fancy lcd display. So i replaced the old with this one, and i noticed that some weird power drains occur when the cpu is not started. For example, the backlight is not working at all until i restart the cpu for the first time. Now when i replaced the transistor,i again tested the sbc at 4MHz, and it is not working anymore, but it does make some weird power drain pulses, because the lcd backlight keeps blinking. As a power supply i use a regular 7805 regulator.