Since I'm at work, and work here is very slow today, I decided to run Thomas' core up against Arlet's (just taken from Github, updated 10/8/11) core, using ISE13.2 and fitting for the smallest Spartan 3, i.e. the XC3S50 100-pin.
I don't have ISE10.1 installed here in order to run a comparative test and post results in the Programmable Logic section.
I did not tweak any synthesis settings as this was done on an old laptop. I used 1 speed constraint for the main clocks. It was based on the delay observed after initial syntheses without any constraints.
Both are in Verilog, but you can tell just by skimming over both codes that there are definately 2 different styles. Still spaghettti to me, but worth looking at. The most notable difference is that the "Defines" instruction is present in Thomas's code and very absent from Arlet's code.
Arlet's used much less resources and max frequency was 67MHz.
But Thomas's max frequency was 75MHz.