Working on the Sim and trying to get the I2C core to wake up. At least now, during synthesis, the SCL and SDA lines are not being optimized out. I have pullups on the lines and have written some simple code to send it the proper bits to activate the core, and send a byte of data, but nothing yet.
For the wishbone interface on the I2C core, I have the CYC and STB lines tied together for the active high CS. In ISim I can see the address decoding is correct and the core is getting the correct data at the correct time. I think I will pursue looking at some internal signals within the core.
On another unrelated note, looking at all my synthesis warnings, I found there was a problem with my ORs module. My registers were only 1 bit wide. I fixed that below.
Code:
module ORs(
clk,
WE,
CS1,
CS2,
CS3,
CS4,
INA,
INB,
INC,
IND,
INE,
INF,
ING,
DO
);
input clk; //cpu phase 2
input WE; //cpu WE
input CS1; //I2C active high enable
input CS2; //PS2 active high enable
input CS3; //SPI active high enable
input CS4; //UART active high enable
input [15:0] INA; //from 4Kx16 Zero Page RAMDO
input [15:0] INB; //from 4Kx16 Stack RAMDO
input [15:0] INC; //from 4Kx16 ROMDO
input [7:0] IND; //from I2CDO
input [7:0] INE; //from PS2DO
input [7:0] INF; //from SPIDO
input [7:0] ING; //from UART2BUSDO
output [15:0] DO; //to CPUDI
reg [7:0] INDHOLD;
reg [7:0] INEHOLD;
reg [7:0] INFHOLD;
reg [7:0] INGHOLD;
// when 8-bit cores are not selected, outputs are zero.
always @(posedge clk)
begin
if (!WE && CS1 == 1)
INDHOLD [7:0] <= IND [7:0];
else INDHOLD [7:0] <= 0;
if (!WE && CS2 == 1)
INEHOLD [7:0] <= INE [7:0];
else INEHOLD [7:0] <= 0;
if (!WE && CS3 == 1)
INFHOLD [7:0] <= INF [7:0];
else INFHOLD [7:0] <= 0;
if (!WE && CS4 == 1)
INGHOLD [7:0] <= ING [7:0];
else INGHOLD [7:0] <= 0;
end
assign DO = INA | INB | INC | INDHOLD | INEHOLD | INFHOLD | INGHOLD;
endmodule
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