I know a good number of you have more experience at more up-to-date design principles than I do, so I beg to pick your brains.

In the past, most of my designs have been for slower systems (<= 4MHz). Now I'd like to up that to 20MHz. So, my questions are as follows:

1) Do ground and VCC planes cause more problems from added capacitance than they solve WRT noise suppression at these frequencies?

2) Do ground or VCC connected inter-trace copper pours help keep the noise down?

3) Hence, which are better, voltage planes, or inter-trace pours, or both?

4) Are there any other critical things I may need to know to avoid grief at these clock frequencies?

Any and all help is appreciated.

_________________
Bill

First thing to consider is your clock source. It needs to be well powered with thick traces and well bypassed first of all. Also, you can't just jump in at 20MHz. I think most here will agree with me that there are so very many other variables that can screw up a design from the outset. You may want to consider either a variable frequency source like a VCO, or have more than a few "can" oscillators you can swap in and out in order to test your design at will.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Thanks E_E. Just not sure that approach will work in a financially feasible way when committing the design to copper. I need to get it right the first time if possible.

I found this:

http://www.altera.com/literature/an/archives/an075.pdf

It goes into techniques for GHz applications and some of it might prove helpful. Still, any actual 'real life' experience will be most beneficial.

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Bill

This is great info, thanks E_E.

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Bill

Exactly what are you referring to when you refer to "planes?" If you mean filled planes on the top and bottom surfaces, those are poison to high frequency digital circuits and should be avoided.

In multilayer designs, "planes" generally refer to inner layers that distribute Vcc and Gnd to the circuit. In such a design, the two planes act as a giant capacitor, as well as electrostatic shields, and hence offer a number of benefits:

1. Virtually no crosstalk between traces on opposites side of the board, especially in cases where traces are coincidental.
2. Greatly improved noise immunity. Due to the large capacitance between the power and ground planes, switching noise is suppressed to an extent not otherwise possible.
3. No ground bounce. The ESR (effective series resistance) of the ground plane is a tiny fraction of an ohm, so stability killing ground bounce is eliminated.
4. Improved Vcc regulation. As with the ground plane, the power plane has vanishingly small ESR, so every component sees the full voltage, and that voltage is as stable as the power source.
5. Better board density. Not having to run Vcc and Gnd traces everywhere means your circuit can fit into less board area (real estate). Aside from possibly reducing the cost of the board, the tighter density helps to keep the signal traces short (see below).

They can under certain circumstances. However, filled planes also added a lot of distributed capacitance, which will distort waveforms at higher clock frequencies.


Inner planes only, as described above.


There are several:

1. Keep signal traces as short and direct as possible. Long traces produce more reactance and cause waveform distortion that can lead to anomalous chip behavior.
2. Avoid circular routing, that is, routing traces so they wind around several pins to which they are not connected.
3. Work with the smallest trace width that is consistent with the current that will pass through it. For most digital work, traces widths can be in the .006" to .007" range, and via should be .025" to .030" diameter. I used .006" inch on my POC unit, with .026" via. It will run at 15 MHz without the SCSI host adapter plugged in. The trace width can become critical when multiple traces run parallel to each other.
4. Limit trace routing to vertical, horizontal and 45 degrees. In my designs, vertical traces are on the component side and horizontal are on the solder side. The side for angle traces is dependent on the board layout, so I really can't suggest anything specific.
5. Arrange your clock signal source so the distance from the source to the chips that use it is approximately equal in all cases. As the frequency increases, slew rate becomes critical. If four chips have short paths to the clock and the fifth has a long path, that fifth chip will be operating slightly out of phase with the others.
6. Be liberal with your bypass capacitors. Every chip should be bypassed and the capacitor should be as close to the chip as possible. Bypass capacitors are cheap. Scrapping a PCB because it suffers from noise-induced instability is not. A good choice for most bypassing is 0.1uF MLCC, with a 50 VDC rating, of the X7R type. The seemingly high voltage rating has to do with a quirk in MLCC capacitors that causes them to "derate" themselves when the instantaneous voltage exceeds the working rating. The result is less bypassing than expected. The particular brand I used on the POC is AVX, part number SR275E104MAA. Scoping the circuit shows that it is dead quiet.
7. Be sure to add some electrolytics to the bypass capacitor roster, including one right at the point where power is applied to the board. Use low ESR electrolytics, with a working voltage as low as practical. Also bypass the electrolytic with a 0.1uF capacitor to assure adequate noise dissipation.
8. If possible, use PLCC and other small outline packages. You'll get a tighter layout, and in many cases, may find trace routing to be easier. When I designed the PCB for the POC unit, I did layouts for both the DIP40 and PLCC44 versions of the MPU (65C816). The PLCC44 part used about 60 percent of the area of the DIP40 part, and I was able to use shorter traces to make the critical address and data bus connections.
9. Avoid chip sockets.
10. Place pullup resistors as close to the device(s) they serve as possible. This is especially important with IRQ, which is wire-ORed and therefore vulnerable to a lazy rise transition due to distributed capacitance.
11. Speaking of pullup resistors, SIP or DIP resistor packages typically insert less capacitance into the circuit than discrete parts (especially carbon comp resistors). Also consider that other leaded components can put reactance into your circuit and possibly sabotage timing.

There may be other items that I didn't think of. Garth may have a few to add to the list.

Something that is somewhat hard to explain is that PCB layout has a sort of feng shui to it, which becomes obvious after you've played around with it. Owing to the way certain packages are pinned out and the relationships between the components in your design, parts positioning tends to develop a natural flow. I really don't know how to explain it, anymore that a musician can clearly explain how to get music from an instrument.

In that respect, I'm reminded of an incident that supposedly occurred while J.S. Bach was instructing one of his organ students. The student was having trouble with one of Bach's pieces and finally Bach, who was reputed to have less than ideal patience, sat down at the organ and started playing. "See," he exclaimed to his student," all you have to do is press the right keys at the right time and the organ will make music." Hopefully your board design will flow as easily as Bach's music did from his mind and hands

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks folks, much very good information. I've got some study and experimentation ahead.

_________________
Bill