Hi all,

this entry is related to the discussion about a 65C02-based PC under the topic "General Discussions". Unfortunately there are of course many different wishes and opinions and therefore after about one year no practical results.

So I have designed a small PC with a WDC 65816, running at 14 MHz. After RESET it is slowed down by the factor 8 to allow the ROM to be copied into RAM. After that the system can be run at 14 MHz. On board are 512 KB of RAM, two WDC6522 for parallel I/O and a SCSI-Interface. I chose SCSI, because I have got some hard drives of this kind, but an IDE-Interface should be also easy to implement. There are 3 expansion slots for add-ons. Access to this slots occures at a speed of 0.875 (14/16) MHz to avoid problems with higher frequencies. I plan to use one slot for an old 6845 based video board, I still own. If you don't like that, use any other . It should even be possible to adapt an old ISA VGA card. Another slot is reserved for an ethernet interface card. I'm planning to connect it to a ISA ethernet card with a Realtec 8019AS chip. The remaining slot will be used for additional I/O, may be floppy (ancient, but still functioning ) or some kind of memory card. The memory chips are cache chips of an old 486 computer. For the logic chips I use 74Fxx, just because I have got them. 74HC(T) will be too slow. 74AC(T)xx might be o.k., but I couldn't check it out, because I haven't any. My prototype computer works stable. You can find the schematic at:

www.deboy.de/pc65816/pc65816.pdf

The AT keyboard interface is placed on an additional board and includes a realtime clock chip RTC58321. The keyboard interface is similar to the interface of Lee Davison on this website, but uses IRQ:

www.deboy.de/pc65816/atkeybd.pdf

Currently I'm starting with the programming of the ROM software using the cross assembler AS of Alfred Arnold.

Any comments are welcome.

[b]Edit[/b], 1/25/12: The new link is http://www.pc65816.de/ .

Wow-- 50 ICs! That's a lot of wire-wrapping, or board lay-out, or something!

Did you determine for sure that the 74HCT541's on the address lines were necessary? I think WDC's '816 has the same output buffers their 65c22 does, which will sink or source 50mA into a short, and pull down to .75V with 24mA. The 74HC bus-driver outputs on the '541 do have a somewhat higher current capability.

Did you try running it any faster than 14MHz? I wonder how much "safety margin" there is there, since I ran into trouble before (on paper) with the latching of the high address byte. WDC's specs here do not guarantee operation at the higher speeds with the sample circuit they show in the data sheet, since the latch signal on the equivalent of your IC1 does not transition until after the high address byte may be gone from D[0...7]. I'm curious about your diode, resistor, and capacitor there, especially since the 3.9pF capacitor may be less than IC1's input capacitance anyway, and almost certainly less than that of the whole net with other stray capacitances on the board.

Where is SLD1? I was not able to find it.

I do like the idea of keeping the VIAs on the same clock frequency all the time because I use the timers controlled by phase 2.

I would recommend adding at least one more VIA, if not two. The added complexity would be a very small proportion of what you already have, and a computer like this should not have its usefulness on the workbench limited by so little general-purpose I/O.

Initially it appeared that you had several timing violations, but further examination convinces me that you did your homework and it looks like you have a pretty clean design. Still, it would be good to push the frequency until things start malfunctioning to see how much leeway you have, since the capacitive bus loading is kind of heavy with about 12 loads on A[0...4] and about 16 on D[0...7].

Keep us posted on your progress.

Hi Garth,

Garthwilson wrote:
Did you determine for sure that the 74HCT541's on the address lines were necessary?


Not really. First I used 74F541 as buffers, but the output signal wasn't very good. So I tried the 74HCT541 and the output signal was much better. As the timing of the address lines a0..15 is not very critical, I decided to leave them in the circuit.

Garthwilson wrote:
Did you try running it any faster than 14MHz? I wonder ...


My first idea was, to run it at 16 MHz. Somehow it worked at this speed, but not very stable. At 15 MHz there was no such problem and I am using 14 MHz to keep it safe. For the ROM I use an EPROM simulator and it seems to produce some problems at higher speeds. My PCB design might be a problem, too. The GND and VCC connections were not wide enough and I had to add some external wires. Using Lee Davison's NOP Generator the circuit runs at 20 MHz, but there is no need for a bank select and I would expect there a problem.
During my first experiments I didn't use the circuit D2, R41 and C16. It wasn't even implemented on the PCB. Because the direct connection between pin 2 of IC4 and pin 11 of IC1 didn't work, I used my scope and experimented with some circuits and the one with the 3 parts worked. I soldered them directly to pin 11 of IC1.

Garthwilson wrote:
Where is SLD1? I was not able to find it.


Sorry, the net SLD1 is not labeled in the schematic. It is at pin 6 of IC35B. Net SLD2 is at pin 8 of IC7C.

My original idea was to use 4 different speeds:

16 MHz for the 512kB cache RAM, the 6522 and the SCSI-Controller
8 MHz for additional 3,5 MB RAM of the type 628512-55
2 MHz for the EPROM
1 MHz for the expansion BUS

Since the design got bigger and bigger and I wanted to use an old external SCSI case with limited space, I reduced my original design. So there is a little bit waste logic, especially in the slow down circuit.

Garthwilson wrote:
I would recommend adding at least one more VIA, if not two.


Adding more 6522 is pretty simple, if there is no need for an interrupt. IC26 is prepared to address 6 more pieces.

I would like to put the 74-IC's into one or more FPGA's, but I have no experience with this kind of design. Is there anyone on the forum, who has and is interested to do so?

Regards,
Joachim

> My first idea was, to run it at 16 MHz. Somehow it worked at this speed,
> but not very stable. At 15 MHz there was no such problem and I am
> using 14 MHz to keep it safe.

IOW, there's really not much safety margin. That little bit of margin may easily be used up if the circuit has to work at a higher temperature or if one gets parts that are slower (even if they're still within manufacturer's specifications).

Something that came to mind after my last post and may need some scrutiny is the clock circuit. Especially with everything spread out on so many pages and the fact that I'm not familiar with it all as you are, it would take me more time. What I'm thinking of is the possibility of glitches. For example, with the matter of changing the clock speed on the fly, possibly as much as hundreds of thousands of times per second, could there be trouble from a CPU_CLK high pulse for example of only say 5 ns a little ways into what should be a 36ns low time? Is there any possibility of producing something like this based on switching between clock signals derived from flip-flops and gates with different amounts of accumulated propagation delay? Something like this could start causing random crashing or other difficult-to-troubleshoot errors when you start getting the SCSI and expansion slots going.

As for programmable logic, you don't need to go to the extent of an FPGA. CPLDs are a nice step above something like a GAL, offering a lot more capabilities. Cypress has a good line of CPLDs with timing that's more predictable than that of other manufacturers, and the software is free when you buy the $200 programmer.

IMHO the clock generator and the slow down logic will work properly, as long as the slow down signal is asserted early enough, i. e. within phase 1 of clock. The most critical part for higher frequencies is the latch circuit for the addresses 16..23. Since a23 is used for /SLD1, there is just a small gap for the slow down logic to react.

To optimize the latch circuit, I have ordered some parts, for example a delay line circuit, where I am able to access the signal in delay steps of 2.5 nS and a 74FCT373 as the latch circuit. When I get the parts, I will try some things out and then post the results.

For my own 65816 PC concept design (see http://www.falvotech.com/cgi/fsforth/ForthBoxKestrel), I have designed a 68000-like, 3-phase asynchronous bus interface for the 65816. I needed it, because I needed zero wait-states when accessing RAM, precisely 1 wait-state when accessing the video shift register (this gives the MVN instruction 8 cycles per byte moved instead of seven, thus perfectly matching the video shift rates), 4 cycles when accessing EEPROM (safety margin), and arbitrary number of wait-states when accessing the VIAs.

Note that I have only 5MHz rated VIAs; since I only have two such VIAs in my posession, there is no fear of this aspect of the design entering the production units. Still, the slow-down logic for the slow VIAs is not complex.

The asynchronous bus logic is much simpler than the logic I saw on the PC65816 schematics for clock stretching. It might be of general interest. If anyone wants any details, I'd be happy to provide them. They can go in with the rest of the other mini-HOWTOs on this site.

Because I'm an amateur and not an engineer, I'm rather sure, that there are better ways to do the slow down.

I'm very interested in your solution. Would you kindly publish the schematic ?

Since I need to document this circuit thoroughly for my own 65816-based kit that I'm hoping to sell someday, I certainly will. However, it might take me a few days to do. I'll let you know when I finish it where to access it.

--
Samuel A. Falvo II

As this might be of general interest, I started a new thread on the asynchronous bus logic.

I'm really an amateur but i've been wonering and researching for some time now about a PC-like architecture for old processors and between some ramblings i got to the teory of a multiprocessor enviroment, 6502's & 65816 are actually cheap (in my country about 10 dollars each, if you buy only one in the most expensive place), so i got to the teory of a shared memory with a buffer between processors desfaced each so that you dont have share problem (or maybe a couple of flip flop so the same impulse two times do not create a problem but i've been a little ovwerwhelmed for the need of making most of my circuits by hand (IC's are hard to get and expensive, besides they cannot be repared), for now i'm focussing my atentions in ADC fast enough to eliminate the ROM and only use tapes (with an algorythm a little carzy i created, that's what i do i program, in hardware i'm really a newbie) so if you have any thoughts or share schematics (blairpossed@mailcity.com - no curses please i know that is a bad message ) . greetings

I've been reading about your computer that you built. It seems quite impressive. I'm embarking on a computer build project as well now, although I will probably take a bit of a different path in hardware then you did.

I do have a question tho, as I was curious about how you are transfering your rom program to ram for full speed operation - are you using the memory transfer function of the '816, and are you transfering it to the ram that is in frameset0, or another frameset?

I noticed you said that it is working in a stable manner, have you tested the scsi interface? Have you stored files or an OS on the scsi drive yet for your computer? Also how were you planning on interfacing the ethernet into the system? You mentioned using an older ISA card, where did you find the information to make it so you can use that card (ie connections and writing a driver for it)?

I think in my endeavor I will probably go the ide route rather then scsi, but I am honestly not sure yet.

Pretty cool development so far, looking forward to seeing pics of it =)

-T

_________________
-Tony
KG4WFX

Yes, I use one of the block move commands and the ROM content is written to bank 0. The part of the rom program doing so looks like that:

REP #$30 ; DATA AND INDEX 16 BIT
ASSUME X:0, M:0
; MOVE ROM INTO S-RAM
LDA #$FFFF ; FILL C WITH X'FFFF'
LDX #0 ; AND INIT INDEX REGISTERS
LDY #0
MVN 0,0 ; MOVE 64K ROM INTO S-RAM
SEP #$30 ; DATA AND INDEX 8 BIT
ASSUME X:1, M:1
STA WARP ; SWITCH TO LIGHT SPEED


I understand, if you prefer ide. It's much cheaper and SCSI devices are a bit exotic nowadays. But I own some SCSI harddisks with a capacity from 540 to 4500 MB and it would be a misdeed to keep them aging in my drawer.

The interface worked fine with a SCSI-2 device (IBM DSAS-3540), but I encountered problems with new SCSI-3 drives (for example Quantum Atlas II XP34550). For this reason I did some modification: The latch for the scsi_reset and scsi_select signals is now a 74374 to get a well defined output signal during the latch selection phase. The other change to the interface is the addition of a scsi_atn line. This allows sending messages to the scsi device, a feature which is needed for better device control. With this modifications I read a block of the SCSI-3 device. So I think, the interface is o.k. now.

I chose the Realtec ethernet chip, because I found a quiet simple instruction to interface it to micro computers on a German website. Because I don't like soldering smd devices and to save the investment in the ethernet transformer and the other parts, I decided to use a ready-to-use ISA-card. But I haven't tested it yet.



I put some photos of the original design into the web:

http://www.deboy.de/pc65816/pic1.jpg
http://www.deboy.de/pc65816/pic2.jpg

The part in the rom socket is an eprom simulator. For CRT output I'm currently using an existing old 6845 based board, which is connected to the slot via wires and placed beside the power supply. On top of the power supply the network card is mounted.

Joachim

As I promised in an earlier post I did some modification to my computer and checked out, if it runs at higher speed. The first modification is the use of fast CMOS devices for the address buffers. Then I changed the direction of the data bus buffer IC2, because the b-outputs have a higher driving capability. The bank latch is now a 74FCT373 and the enable circuit is modified. The latch now keeps the bank address a bit into the next phase 1. I changed that to eliminate small spikes ( about 0,7 V) directly after the latch phase, if there was a logical 1 on the data bus. The addresses signals 16..23 are now very clean.

Now the bad news:

The computer nevertheless doesn't work at higher speed. The reason is, that all my cpus stop presenting the multiplexed bank select signal on the databus at higher speed (i.e. 16 MHz). So I will continue with 14 MHz, the speed for which my chips are released.

The keyboard interface changed a bit, too. I inserted the possibility to suppress the keyboard clock, thus allowing to stop the keyboard communication to ignore no keyboard data, while interrupt are disabled.

The modified schematics can be found at

http://www.deboy.de/pc65816/pc65816.pdf

http://www.deboy.de/pc65816/ATKeybd.pdf

Next I will do is to write the rom code.

Joachim

Hi

I was wondering, why not add some nv ram chips, would that not be a worthwile idia for the OS? trythe ds1265ab-100, they are 8mbyte and are easy to work with a latch.

And what about a tv output? (like rca)


I would have added something like this if I could, but the problem is I do not have enough knolage about these things, I am still only 14, and thus I work on a low budget too.

I have access to someone who can make pcbs for me, so the wireing isn't a prob.

edd