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PostPosted: Wed Oct 05, 2011 6:20 pm 
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Dr Jefyll's "coprocessor contraption" featured yesterday on Hacker News

Here's a short summary by the submitter:

0x12 wrote:
Guy expands 6502 to 16M address space by intercepting the databus and re-mapping unused opcodes and clever use of the spurious signals generated by the cpu when executing other undefined opcodes, adds a few registers to make the whole thing transparent from an assembler programmers point of view. In other words, there is no difference to the programmer between native and newly minted instructions.

On top of that he boosts the speed of his forth interpreter by concentrating on a frequently used construct called 'NEXT' in a way that should make anybody that has tried to optimize the inner loop of some VM or language proud. After all, what better way to optimize in such a situation than to be able to mold the instruction set to your desire.

He then uses this home-brew Frankenstein contraption as his benchtop computer for multiple years to do real work (instead of just shooting some pretty pictures and calling it a day).


Nice!


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PostPosted: Wed Oct 05, 2011 11:10 pm 
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Excellent, Dr. Jeff has made it to the big time! Congratulations :D

I was always intrigued by Dr. Jeff's opcode 're'-definition, even though it was made specifically for Forth.

As the days pass on, I for one am becoming more interested in Forth.
It seems the best and brightest here use it/are using it as a higher level language.

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PostPosted: Thu Oct 06, 2011 3:58 pm 
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Thanks for noticing, fellas. I was pleased when I got an email from someone notifying me of the Hacker News posting. But I was gobsmacked later when I looked at the web site stats! In one day, four thousand visitors loaded 12,000 pages! That's more traffic than I've had in the last year !

on Hacker News, 0x12 wrote:
Guy expands 6502 to 16M address space by intercepting the databus and re-mapping unused opcodes and clever use of the spurious signals generated by the cpu when executing other undefined opcodes, adds a few registers to make the whole thing transparent from an assembler programmers point of view. In other words, there is no difference to the programmer between native and newly minted instructions.

On top of that he boosts the speed of his forth interpreter by concentrating on a frequently used construct called 'NEXT' in a way that should make anybody that has tried to optimize the inner loop of some VM or language proud. After all, what better way to optimize in such a situation than to be able to mold the instruction set to your desire.

He then uses this home-brew Frankenstein contraption as his benchtop computer for multiple years to do real work (instead of just shooting some pretty pictures and calling it a day).

I'm grateful to this 0x12 person for his succinct summation of the project. My own web site sorely lacks such a summary. :oops:
Edit: Summary subsequently added, here. The full story can be found here. See also the 6502.org topic begun in 2009, 6502 Forth with hardware accelerator.
Edit: diagrams added


ElEctric_EyE wrote:
I was always intrigued by Dr. Jeff's opcode 're'-definition, even though it was made specifically for Forth.

The Forth aspect is probably not the thing that folks will find most interesting. The big news is efficient access to a flat 16 MB address space. As noted on my site, the op-code redefinition is a trick I stole from Don Lancaster. He used it to create an instruction that output video. My goal was to take the idea to a whole new level. 8)

-- Jeff
http://LaughtonElectronics.com


Attachments:
KK Register Diagram.png
KK Register Diagram.png [ 8.39 KiB | Viewed 2341 times ]
IC-function layout.png
IC-function layout.png [ 31.66 KiB | Viewed 2341 times ]


Last edited by Dr Jefyll on Sat May 13, 2017 2:20 am, edited 2 times in total.
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PostPosted: Thu Oct 06, 2011 4:24 pm 
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Dumb question, is your schematic released on this clever design and can it work out in a CPLD? Reason I ask, still working on my Pinball Mind project and it is planned with a CPLD memory manager system as a bank switched rom system. I will put up the schematic tonight, want to see your thoughts in migrating it over, create your own version 2, as it were.

Mad props to a helluva design of yours, period....

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PostPosted: Thu Oct 06, 2011 4:58 pm 
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Hi, Tony! Thanks for your interest.

Let me start by saying that I have LOTS of ideas in this same general realm. These include a 65816 co-processor/accelerator (beginning with "smart" memory in Zero Page), and also various takes on 6502-ish and Stack Machine cpu cores. The main limitation is time. I am self-employed and need to maintain a balance between work-work and play-work! :D

More specifically, no -- the KimKlone schematics are not available unless I scan the paper originals. The good news is that, using modern programmable logic, you can certainly come up with a better solution than bank switching!

I am limited for time at the moment, but we can follow up on this. If you've read the article carefully then maybe you'll already be getting some ideas of your own!

cheers,

Jeff


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PostPosted: Thu Oct 06, 2011 5:08 pm 
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I did which is why I asked. My original design idea was a simple bank switcher within the CPLD logic. The board itself has the 65C02, 65C22 for a VIAUSB port, 27C256 for 32K main rom 32K main ram, and extra sckets for 4 meg bank switched rom and 4 megs bank switch RAM.

I also tried to squeeze out every last bit of memory space to usage as follows:

$0000-$5FFF 24K RAM (in the main ram)
$6000-$7FFF 8K bank switched space (128 pages of RAM, 128 pages of ROM
$8000-$80FF Rom ID/IO area
$8100-$FFFF 32k - 256 bytes ROM

The IO bank would have internal registers, 16 bytes for the USB 65C22 and would go out from there. Tentative registers:

00 Bank switch address: write in here.
01 Bank switch address mirror: read here for status
02 Rom ID area pointer: write 00-ff here to address the rom ID under the IO area
03 ROM ID resultant: read here for data from ROM ID area
04 post LED and other stuff


The schematic I hope is simple and elegant in the design scheme. hope it can jump start you for a rev 2 of your design.



For me, got full time work plus several side gigs going. This is for a pinball computer and since I already had the controlling CPLD in mind, it was trivial as heck to add 2 more sockets for bank switched memory. the board is also generic enough to use for most anything.... one of the neatest uses planned for it was for an airplane lights controller....

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PostPosted: Thu Oct 06, 2011 5:45 pm 
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Hmmm. Naturally I'd love to cook up a solution, but I can't help asking: what if anything stops you from just using a 65c816? At first glance it seems to me to be "the shortest distance between two points."

The next question is, will your expanded address space be filled with code or data or both? Or do you view it as just a general resource, usage unspecified? Finally, do you anticipate a need for large (>32K, say) data arrays?

-- Jeff


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PostPosted: Thu Oct 06, 2011 5:48 pm 
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I don't know the 816 as of yet. One goal is for people to be able to replace the parts fairly easily. Though come to think of it, the 816 is easy to come by on ebay by getting a GS on there. Lot more 65C02s hanging round I figured...

(the original pinball mpu used a Fairchild F8 embedded that cannot be repaired, this will become a piggyback for it. Look up the Bally home Fireball pinballs...)

the extra memory is usage unspecified for future programmers to add things like deeper rules or possibly video or other unknown usages. The present code I do have that gives me an attract mode is 4K so far and should fit within the 32K rom. the cost of 2 sockets and some unused pins on the CPLD, it gives me more space to play with. This also came about from a proposed airplane lights computer upgrade I am doing. (check out www.americanairlights.com, the new proposal will use a different system though).

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PostPosted: Thu Oct 06, 2011 6:02 pm 
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Re: 65c816, there are many on this forum who could advise you better than I. But it's safe to say there's a lot you could learn but very little you would have to learn. Since your goals are a fraction of what the chip is capable of, I bet the learning curve would be no worse than whatever hoops you jump through when dealing with any banking scheme! Also I seem to recall someone mentioning that WDC has improved their vending to small consumers, so I doubt that sourcing the '816s would be a problem.

The F8 replacement project sounds like an interesting challenge, BTW... :D

-- Jeff


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PostPosted: Thu Oct 06, 2011 6:19 pm 
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http://www.nightmarepark.com/6502.php?d ... ll%20Mind/

the picture has my first board prototype which is a modified version of Darryl's SBC-1 to run. The middle is the interface to the old socket and the other would be a sound board. the video is of the code running the display animations. If you want, I will email you the code or just place it in there tonight as well.

going 816 I had not thought of but it can run 65C02 code in mode, so the code is already portable. Let me see how cost compares and all.

http://www.ipdb.org/search.pl?any=fireb ... quick#4116

there was 4 pinballs sold with this Bally Brain mpu, fireball, captain fantastic, evel knievel and galaxy ranger.

2 factors I am also thinking in the migrate, chip cost and also familiarity. The 65C02 was used in quite a few arcade games, so it is familiar to the repair types while the 816 was quite rare in the arcade field.

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PostPosted: Thu Oct 06, 2011 6:43 pm 
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Quote:
going 816 I had not thought of but it can run 65C02 code in mode, so the code is already portable. Let me see how cost compares and all.

It won't give you the illegal op codes of the NMOS 6502 because the whole op-code table is full with new instructions and addressing modes. For 65c02 code, the only instructions it does not have are BBS, BBR, SMB, and RMB, but most 65c02 code does not use those since most early 65c02's didn't have those four. The '816 in native mode is easier to program however when you're constantly dealing with 16-bit quantities (like data cells and addresses).


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PostPosted: Thu Oct 06, 2011 6:47 pm 
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I already had gone from 6502 to 65C02 for this, so illegals are not a problem. I do not use the opcodes you mentioned, so migration should not be a problem. Cost is minimal but for others to service the system I am more concerned with. Wonder how hard is it to have some kind of jumpers to allow either an 02 or an 816 to be plugged in....

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PostPosted: Thu Oct 06, 2011 6:53 pm 
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Quote:
how hard is it to have some kind of jumpers to allow either an 02 or an 816 to be plugged in....

If you're just designing the board now, it's very easy since most of the pinout is identical.


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PostPosted: Thu Oct 06, 2011 6:56 pm 
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Am designing it now, the schematic is complete, I plan to post it tonight in my folder along with the code for Jeff.

EDIT: spent 10 minutes comparing to Darryl's SBC 4 pinout on the 816. The changes are pretty minor, connecting 5 previously open lines and a jumper for pin 1. the CPLD code would change depending on what is used anyways, so this minor mod will work. Thanks on the brain gig, Garth and Jeff!

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PostPosted: Thu Oct 06, 2011 8:55 pm 
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Nightmaretony wrote:
I don't know the 816 as of yet. One goal is for people to be able to replace the parts fairly easily. Though come to think of it, the 816 is easy to come by on ebay by getting a GS on there.
...


Not necessary. Jameco carries the entire WDC line, including both the DIP and PLCC 65816:

http://www.jameco.com/webapp/wcs/stores ... 2143662_-1
http://www.jameco.com/webapp/wcs/stores ... 2143671_-1

Toshi


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