I think I was already reserving space for 4 registers, but never used more than 2. Feel free to change into.

Also, I noticed the code defines a BASE_ADDRESS, but never uses it. Instead it relies on an external select signal. The BASE_ADDRESS parameter can be removed too.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Usually you'd write that as



Correct.

By the way, the UART wrapper does not set DO=0 when it's not selected, so you can't simply OR it together with other peripherals. You either need to put a wrapper around it that will take care of generating the 'sel' signal, as well as setting DO=0, or modify the uartif.v code so that DO=0 when !sel.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Thanks - just done my merges, I'm all up to date with your core now.

I had to do one additional change - you seem to have dropped an 'end' in the fix to the I reg update.

EEye: I haven't picked up any of your work in git, as our code has diverged quite a bit - mostly in small ways, but it makes it fiddly to see where the interesting differences are. I think we have
- you removed BCD textually, where i used defines
- you also removed SED and CLD, and the D flag
- you did a lot a reformatting
- you init the stack pointer and registers
- you re-indexed AXYS
- you did some additional change from <= to = (in cond_code, on June 8)
- finally, you added PHX, PHY, PLX, PLY (again, without defines)

Those last three changes I think I'd like to pick up on. I'm not sure I have the git commands to do that by inheriting your history. I think I need cherry-picking.

Generally, I would like to add some 65C02 instructions, but I'd do it with defines to make them configurable. (Just as I keep BCD, but as a configuration option.)

First though, I think I need some kind of debug port, maybe with single-stepping using RDY, because something isn't quite right with my SoC.

Cheers
Ed

Thanks. It's been fixed now.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hi


Yes, understood - I wasn't criticising, just cataloguing. On github you'll see there's a button 'Fork Queue' which shows how far out of sync you are with other people on a project. It's meant for the case where the different forks are trying to stay together, which perhaps isn't quite what we're doing. But it does show the various differences.


I'm not sure what the best tactics are, to be honest. What you can do in github is one thing, and then there's what you can do in 'git', the tool itself, which is a lot more powerful. You could I think make a 'version release' just before you started to add the 65c02 instructions. But I think to do that you need to use the git tool - I don't think you can do that just by pushing buttons in github.

Again, this is something you can do if you run the 'git' tool on your computer, but that can be quite an intimidating thing do to. Because the history of the project is always kept, it's still possible for you or anyone to pick up the state of the sources just before you started adding the 65c02 instructions.

Or you could take the state of cpu.v at that time and copy it, and check in the copy. Again, not sure if you can do that purely using the github web interface.

Right - but I meant the git command git cherry-pick which takes a particular change from someone else, and applies it to your project knowlingly - it has the author and the timestamp of the original change. Probably overkill for what we're doing, but formally I think it's the way a tool like git is supposed to be used.

Unfortunately, trying to do things the right way can have the effect of slowing things down and making them more complicated - so feel free to ignore all these considerations!

Cheers
Ed

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I wouldn't normally be enthusiastic about starting over - the strength of a revision control system like git is that it keeps track of history. Usually better to go where you want to go, starting from where you are now.

But I think there are a couple of tactical questions to decide before proceeding,

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65Org16:https://github.com/ElEctric-EyE/verilog-6502