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GARTHWILSON
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PostPosted: Sun Aug 28, 2011 4:16 am 
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It's a USB to TTL module, but if I got it right this module does not have any clock input or output, so how do I connect it the to the 6850(or elsewhere)??? [English fixed]

It is a USB-to-RS232 converter, but lacking the line drivers and receivers.  Without the line drivers and receivers, you could connect it directly to one of the UARTs you've talked about.  Connect:
its TD to your RD,
its RD to your TD,
its RTS to your CTS,
its CTS to your RTS,
its DSR to your DTR,
its DTR to your DSR.
You can probably get away without RI.

RS-232 is asynchronous, meaning there's no clock line.  The two ends have to agree on the speed, then the receiving end starts its clock at the leading edge of the start bit for each byte, and just uses the timing to know which bit it is looking at at any given instant.  That's why the timing has to be accurate with RS-232.  Edit: I blew the dust off an RS-232 primer article I wrote 9 years ago but never did anything with, and updated some links and things and posted it on my website, at http://wilsonminesco.com/RS-232/RS-232primer.html .

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Last edited by GARTHWILSON on Thu Apr 05, 2012 7:42 am, edited 1 time in total.

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Dajgoro
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PostPosted: Sun Aug 28, 2011 2:47 pm 
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So, how do i connect it to the 6850? Do i put on the clock input the exact clock of the usb/ttl module? Will it work?
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GARTHWILSON
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PostPosted: Sun Aug 28, 2011 7:37 pm 
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You will need a separate oscillator for the 6850.  What I get from the 6850 data sheet at http://pdf1.alldatasheet.com/datasheet- ... C6850.html is that bits 0 and 1 of the control register select whether to divide the transmit and receive data input clock signals by 64, 16, or 1.  So for 9600bps and a ÷16 for example, the input clocks would have to be 153,000Hz.  If you start with a 1.8432MHz external oscillator, you'll first have to divide it by 12 externally to get 9600bps that way, or by 3 if you use the 6850's ÷64 mode.  The 6551 has the oscillator onboard and uses a standard 1.8432MHz crystal for all standard baud rates up to 19.6kbps and you set the bit rate internally through software.

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Dajgoro
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PostPosted: Sun Aug 28, 2011 9:56 pm 
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Well, i only have the 2.4576MHz crystals and the 4060 counter for the 6850 clock.
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GARTHWILSON
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PostPosted: Mon Aug 29, 2011 12:05 am 
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So then you will have to make an oscillator with the 2.4576MHz crystal, and divide its output by 16 and tell the 6850 to divide by 16 again to get 9600bps. The divisors can be changed of course for other rates.

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Dajgoro
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PostPosted: Mon Aug 29, 2011 4:39 am 
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Ok, great, i hope i get the crystals soon, i will post my progress...
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Dajgoro
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PostPosted: Sun Sep 04, 2011 11:38 pm 
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Since i don't need modem signals(cts rts dcd), what do i do with them on the 6850?
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GARTHWILSON
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PostPosted: Mon Sep 05, 2011 12:08 am 
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I just pulled down my old Mot data book covering the 6850 from the top shelf (9 feet up), and was surprised to find the 6850 does not have DTR\ or DSR\, let alone RI.  (In addition to RTS\, CTS\, and DCD\, the 6551 has DTR\ and DSR\ but not RI.)

Even without involving a modem, hardware-handshake signaling on RS-232 require RTS and CTS.  If you don't need the DCD\, just ground that input.  If you're going to use XON/XOFF software handshaking, just ground the CTS\ input also.  You will probably want to use pin jumpers or DIP switches though, so you can set it back to listening to the CTS line of the RS-232 if you want hardware handshaking at a later time.

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BigDumbDinosaur
PostPosted: Mon Sep 05, 2011 3:37 am 
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GARTHWILSON wrote:
I just pulled down my old Mot data book covering the 6850 from the top shelf (9 feet up), and was surprised to find the 6850 does not have DTR\ or DSR\, let alone RI.

Actually, omission of DTR and DSR is fairly common, as there is no particular requirement for these signals. CTS and RTS are important if data rates are to exceed 9600 bps, since XON/XOFF handshaking above 9600 becomes unreliable in many situations. Incidentally, I did provide a DTR output on both ports of my POC unit but nothing that is connected actually requires it.

RI is also of questionable value. I looked at the Equinox serial hardware in my Linux box and determined that while RI is connected and is monitored by the Equinox driver, getty doesn't act upon it. DCD is definitely of more value if a modem is involved. If not, it should be tied to ground. Allowing it to float may cause spurious interrupts.

One thing the 6850 does offer is higher maximum data rates. Dunno how that is important to Dajgoro.
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Dajgoro
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PostPosted: Mon Sep 05, 2011 3:26 pm 
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One thing the 6850 does offer is higher maximum data rates. Dunno how that is important to Dajgoro.


Well you just said why...
And i was looking in the 6850 datasheet, when i saw there is a bit in the register which acts like a reset. So when the 6502 restarts, can it just enable that reset bit, instead of cutting power to the 6850 for the reset?
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GARTHWILSON
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PostPosted: Mon Sep 05, 2011 4:23 pm 
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That seems to be the only way to reset the 6850, as it has no RST\ input either, and no power-up reset circuit.  You have to write 0's to CR0 and CR1 to reset it, including in your power-up reset routine.

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BigDumbDinosaur
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PostPosted: Mon Sep 05, 2011 11:13 pm 
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Dajgoro wrote:
Quote:
One thing the 6850 does offer is higher maximum data rates. Dunno how that is important to Dajgoro.


Well you just said why...
And i was looking in the 6850 datasheet, when i saw there is a bit in the register which acts like a reset. So when the 6502 restarts, can it just enable that reset bit, instead of cutting power to the 6850 for the reset?

Right...it's referred to as the "master reset."
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Dajgoro
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PostPosted: Mon Sep 05, 2011 11:24 pm 
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I found this:
http://www.compeng.dit.ie/staff/tscarff/6800/6850acia/6850.htm
Do i put the second phase clock on the enable input and the other select signal to the chip select pins... (Sorry for all the questions,i never done anything with serial communication before)
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BigDumbDinosaur
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PostPosted: Tue Sep 06, 2011 2:03 am 
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Dajgoro wrote:
I found this:
http://www.compeng.dit.ie/staff/tscarff/6800/6850acia/6850.htm
Do i put the second phase clock on the enable input and the other select signal to the chip select pins... (Sorry for all the questions,i never done anything with serial communication before)

My memory is hazy on this, but I seem to recall that the correct way to use the E input (chip enable) is to wire-AND it with Ø2 high. E, in other words, would be connected to the output of a two-input AND gate. One input on the gate would be connected to Ø2 and the other (possibly through an inverter) to the chip select signal generated by a '138 or similar. The CS0, CS1 and /CS2 inputs would be controlled by address bus signals. Selecting the chip would have no effect until Ø2 goes high.
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GARTHWILSON
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PostPosted: Tue Sep 06, 2011 2:53 am 
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I see now in the data sheet that for the 1MHz 6850, the CS lines need to be valid at least 80ns before E rises; so yes, E would definitely have to be gated by phase 2, whereas the chip selects must not be.  For the 1.5MHz part, it's 60ns min, and for the 2MHz part, it's 40ns.  You could probably run phase 2 directly to the E input by itself.  As long as the CS lines are not all true, it won't do anything.

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