I'm trying to get an IDE interface working on a 6502-based computer. All the designed I've seen on the web decode p2 as part of the selection logic. The computer I'm designing for - the BBC - does not have p2 available. It only has a signal called 1MHzEnable, which is essentially p1in. Using 1MHzE I can consistantly read the IDE registers, but any attempt to read from a sector repeatedly gives the first byte. It looks like I need a p2 look-alike signal. Staring at timing diagrams it looks like I could invert p1in and delay it by 1/4 cycle to create a signal that looks like p2. Anybody any idea if this would work, and how would I generate that 1/4 cycle delay?

Thanks

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