I have completed assembly of my SBC-4 Prototype. Preliminary results look great.

As some may recall, I had proposed a modular computer that had a main board and stackable modules containing individual I/O components.

(You can read that discussion here)

This version uses a 65C816 with 512K of RAM and uses an AVR ATMega162 to load the RAM during /RESET. The ATMega162 can hold an 8k image that gets pushed to RAM. In the future, I will also provide support for using an SPI or I2C Flash module to load larger images.

There is support for 4 32-byte I/O devices. Using this format, you could add two 65C22's to the system under one device select as each only needs 16 bytes.

The base board is up and running at 16MHz. Having a full stack of I/O will increase bus loading and will most like lower the maximum speed to around 8-10 MHz.

My next step is to build some I/O modules and test the overall performance.

There's a little more info up on my website with more to follow as I get time.

http://sbc.rictor.org/
(Select SBC-4 from the Contents Menu)

Daryl

Looks nifty

Are you planning on setting up a group buy for this?

I am working on a few more items but will eventually offer a group buy.

I have my SPI-IDE interface working through the ATMega162. The throughput is not optimal, but it does work well. I have also modified the DiskOS from SBC-3 to work with this model.

I still need to work on a Flash/EEPROM module to allow for boot-loading options.

I am also working on a composite video/pc keyboard module to allow stand-alone operation. Once those are done, it should be ready.

Thanks for asking!

Daryl

Progress has been rather slow as a big work project is taking up a lot of my time. I have the first daughter board (Composite Text Video and PC keyboard) built and am in the process of testing the video. The keyboard will be tested next. Then its on to a serial EEPROM module for loading OS files.

once I'm there, I'll post all of the specs.

Daryl

I think I speak for most of us here, Cant wait!

Video and keyboard daughter board testing is complete!

I received the serial eeproms yesterday and will start working on the code to access them from the main board. I will then build a pluggable module to allow for easy swapping.

As I get time, I will start adding more details to my website.

Cheers!

Daryl

Progress at last. My day job has been keeping me very busy but I have managed to finally complete the AVR Bootloader code. This includes code to read and write 8k to/from the AVR Flash memory and amost the entire bank 0 memory ($0300-$FFFF) to/from a 64kx8 I2C EEPROM. There is also an option to select the default boot source. If I2C is selected but no module is present, the AVR Flash code will be loaded instead.

The SBC-4 Plus main board is fully functional now!

The first daughter IO board (DAU-TERM) is also complete (PC keyboard and 40x25 Text composite video).

The next daugther board is designed but not yet built (65C22 and 65SPI).

I plan on getting the documentation up first before finishing that board.

My job will keep me tied down until late May, but hope to find time here and there to get the docs written.

Daryl

My 4Mx8 5V SRAM module should be ready for it soon too. I've had the boards and parts here for awhile, but have not been able to put in the time to assemble them.

Edit, Feb 2012: Data sheet available here. I just started a company to make things like this on the side to support the group's homebrew computer construction. See http://WilsonMinesCo.com/ .

That's great news too!

I have finally posted some more information about the SBC-4 Plus on my website. It's not complete, but there is more to read finally, including schematics, features, and a few pictures.

http://sbc.rictor.org/

Daryl

Ever since I ventured into 6502.org, your work stood out, especially since had you ventured into Xilinx CPLD's, which was my curiosity at the time...

But I do have 1 question: Why only 4.5MB on the SBC-4(P)lus and not 16MB?

Thanks! It's a matter of bus loading vs. speed. Garth's 4MB module uses eight 512k x 8 chips. To get 16MB, you would need 32 chips. I'm afraid space requirements and bus loading would result in a very large assembly with a greatly reduced top speed. 4MB was the trade-off.

Do you envision an application that needs that much SRAM?

Purhaps SBC-5 might consider the full address space. I think using higher capacity DRAM would help decrease loading, but would require added refresh hardware. What are your thoughts on providing the full 16MB?

Daryl

Are there pictures of this 4Mbyte board?

You could presumably subdivide the busses so that only one bank at a time is exposed to the CPU, to decrease the loading, with some trade-off (time) cost in going through a transceiver and doing the decoding.

But as you say, you need a good reason for needing so much memory before embarking on the engineering. Garth must have something in mind, or he wouldn't be so keen on 32-bit address spaces!

Cheers
Ed

Not an application. Maybe a chunk of video, audio or some other data that has to be modified in some way...

You're probably right about the DRAM. One other possibility, in addition to BigEd's idea, would be to operate at 3.3V and use 8x 2Mx8 SRAMs. Although, SRAMs I've used of this size are power hungry @~250mA each...
Xilinx has DDR(1,2) Memory Controller Cores for the Spartan 3/ Spartan 6 Series FPGA's which may ease the design although I've never used those cores, but once again we're talking 3.3V operation...

If you need lots of memory, it's possible to use an SDRAM + small FPGA. Use the FPGA to implement an SDRAM controller, and use the internal block RAMs as a fast cache. Disadvantage is that you'll lose predictable timing.