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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

A 200MHz 6502?!.... I heard it before and I'm sure I'll hear it again, but jeez that speed is sweet for a 6502!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

BAH! That's nothing! You just wait until I finish my optical 6502 clone...



(j/k; but, were such a device indeed to exist, its maximum speed would be limited the slower of light propegation delay (about 1 ft per nanosecond) of the longest inter-gate distance, or the element with the highest index of refraction. An interesting topic for another day...)

Even at a mere 20 MHz, the old 65C02 clips right along. The '816 does even better when fully exploited.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Indeed, and I think I even have a working conceptual design for a Hardware Object-Oriented Programming Language Accelerator (HOOPLA -- yes, it's intentional. If AmigaOS can get away with BOOPSI, I can get away with HOOPLA!!).

Why must I have so many projects? Why can I not finish one before starting another?

You are thinking within the relativity Laws of Einstein..

Think of a black hole now. Those relativity laws are now under the Laws of electromagnetism, controlling light... a hyper galactic light coil... as opposed to a speaker coil, same principle i think

Ah jeez you got me started. This is WAY off-topic. My apologies

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I was going on about an electromagnetic optical computer. Anyway, I happened across this article this morning:

http://news.yahoo.com/s/afp/20101028/tc ... ogyitworld

China has the fastest computer @2507 trillion calculations/sec, using IC's from the US!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

So true, so true.... :-)

André

Hi Jesari
A few minutes ago we updated the pre-release simulator on the 6502.org website. It's even faster than before, and you can visit a URL like
http://visual6502.org/JSSim/expert.html ... =60&r=0020
to run a program of your choice and see the values moving between the various registers - including registers not visible to the programmer.

You could instead run the included short demo program with
http://visual6502.org/JSSim/expert.html ... loglevel=5

This is the first version to fix the timing control state signals, so you can see the state of the machine: it's not a shift register, but something like it. You should be able to see the overlap of successive instructions in a lot of cases.

You might want to arm yourself with Donald Hanson's big block diagram - many of the same names are used.

If you turn on the chip layout view, you'll find you can also zoom in and explore the values of any signals.

Hope you find it interesting! (Thanks to Barry, Brian and Greg, as always.)

Cheers
Ed

Edit: update links, from pre-production to released version

I find it timely that you mention this; as I woke up this morning, I decided to work through my old bus synchronization circuitry, asking myself, "What if I represented state as a binary number instead of (in essence) a ring counter?" It's doable, but logic becomes much more complex (6-input AND gates versus 2- or 3-inputs).

Interestingly, you are free to assert multiple states at once, as the 6502 does, if you keep your states fully decoded at all times. You can't do that by representing states as a single number. This is essential for supporting pipelining too.

People can really learn a lot by observing how the 6502 handles its state progression. This is a HUGE service to the electrical engineering community as a whole, and 6502 enthusiasts in specific.

I think, as one of the above posters put it, the 6502 should be classified as "pre-RISC", or as I'd put it "proto-RISC". It definitely doesn't meet the classical definition of RISC, but it was developed before RISC (as such) existed.

That said, it does have some similarities to later RISC processors. Such as a small instruction set, hardwired decode logic, pipelining (even if limited), and a precursor to large register sets in the form of the zero page.

But I think the most important point that makes it RISC-esque is that the ISA is elegant. It's my favorite ISA. The only complaint I've got is that the X and Y registers aren't orthogonal. When I'm in the zone, I can fit the ISA in my headspace, which is a good thing.

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@loop: lda (src),y — sta (dst),y — iny — bne @loop — inc src+1 — inc dst+1 — dex — bne @loop

Yes, that is one real good thing. I remember an interview with Chuck Peddle where he said that they talked to programmers what they needed for an efficient instruction set, which the MOS team optimized, where other CPU designers more worked from theoretical considerations. And that approach really shows.

In fact I think the ISA is so elegant that I decided to extend it to a more modern approach. See my 65k project: http://www.6502.org/users/andre/65k/index.html

André

I would argue that the best answer is it's a pre-RISC CPU. The distinction RISC <-> CISC makes sense from the time on when RISC was coined as a movement to counter CISC complexity. Since the 6502 family never suffered from complexity issues, and doesn't use micro-code, I prefer the term "pre-RISC" to "pre-CISC", but you may use either for symmetry.

A wryly entertaining observation!

Welcome, leidner

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html