The RAM on the NEXYS2 board is SDRAM, but equipped with a front-end to make it look like normal, asynchronous RAM. That's why the burst-mode exists. Apparently, these chips go by the trade name "pseudo-SDRAM", or PSDRAM.

Xilinx just released Virtex 6 architecture along side Spartan 6. I don't think Xilinx is discarding Virtex any time soon.

Well, I must admit I've have never done so myself, but that is what I've read. It may depend on the synthesizer tool, and the exact way things are written down so it can recognize it.



Yes, I wrote my own USB client interface for use with an external USB PHY (Cypress CY7C68000). It uses a shared memory interface for slow stuff, and a dedicated high speed data bus for fast stuff (8 bits * 60 MHz). The 6502 would work best with the slower shared memory interface, and is really easy to interface. Just put the other port of the block RAM in your 6502 memory space, and hook up a couple of interrupt/status lines. Here's a link to the source code http://ladybug.xs4all.nl/arlet/fpga/source/usb_client.v. Apologies for the lack of documentation. It's also 5 years old, from when I was just learning Verilog/FPGA stuff, so it probably could use some cleaning up.



If you want to interface a USB stick, you'll need a USB host, which is much more complicated. I would recommend using a simple (micro)SD card, which is almost trivial in comparison. ETA: But if, you have a SD card interface, then why do you still need the EEPROM ? You can put a simple bootloader in the FPGA itself. A single 2KB block RAM should be enough, I think.



Edited To Add.

I meant the original Virtex, and it's not supported with Xilinx's new ISE12+ software which is really ashame the way they drop families like that. Just like the Spartan 2... Everything else above Virtex is in a BGA type package and I can't solder it. If I can't solder it, I can't use it.


When I was looking into USB master cores, they did seem very complicated. Although when I was researching USB controller IC's, I came across a CY7C67300. Seems to have alot of potential even beyond USB...


I guess I won't need an EEPROM eventually. The software I'm working on will be less then 4K when complete. It has 2 font data, display init routine, copy EEPROM to SRAM routine, and a few routines to display characters typed on the keyboard. A simple terminal.

I guess that's all I would need for a bootloader. But I think I would need to incorporate some basic commands as well. Commands that would copy over data from the SD card into system RAM. Or vice versa, for backup purposes. But I'm getting ahead of myself...I can say, all the adapter sockets have been ordered a few days ago, so all this talk is not for naught.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The SD Card controller looks like it's fairly big. At the cost of some more software overhead, you can also replace it with a simple SPI controller, and some GPIO lines for card detect/write protect. Here is a good web page with hardware/software descriptions: http://www.roland-riegel.de/sd-reader/. It's written in C, but it gives a nice working implementation of getting the cards to initialize (which is a bit tricky with all the different kinds of cards now).

Most of that code is for the FAT filesystem. I don't know if you were planning to have that too, but it's going to be quite big on the 6502. Alternatively, you can just treat the SD card as a big binary block, and use 'dd' on a linux host to access the raw data.

Not quite at the FAT file system yet... I was just planning on copying a .65b file from M. Kowalski's assembler, which is a raw binary file with no headers, to the SD card using a X86 PC. Then plugging in the SD card back into the 6502SoC, instead of burning an EEPROM, which brings up an issue I need to research...

Access times on SD Cards and how they vary amongst cards...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

SD is compatible with MMC, and MMC specs state that cards should be able to handle 20Mbps in SPI mode. If you keep it close to 15Mbps for safety's sake, money's good that it should work.

There's a smaller version of the full featured 32-bit core. It's a FIFO core that has an 8-bit WB interface. Although, it only supports SD 4-bit mode. Still looking for documentation of this smaller core, but I did run it through ISE using the XC3S400, which I decided to stick with since I spent $50 on the adapter socket for it.


There seems to be many speed ratings for SD cards, with the read speeds being much faster than write speeds, but...

What I need to focus on now is bootstrapping the 6502 core, and lose the EEPROM altogether as Arlet suggested. I never worked with ROMs inside an FPGA, but I do think I remember seeing the options, now that I'm typing this, when I was trying to INIT some flip-flops to 1's in another thread... The 2 things I do know is the font data is 2K (128charactersx8bitsx2fonts), and the actual code is less than 1K. I think I could trim the font data...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I see now, I have to use the core generator to make a distributed memory which is easy enough. Everything is automated. Made a 4Kx8 ROM, and it automatically makes a symbol.

Now I have to see how to make/edit a .coe (coefficients) file which will be the addressed contents in the ROM...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

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It's 4am, was back at it. So far, had success making a top level schematic and placing a 4Kx8 ROM. Was able to get to the memory editor from ISim, but there's no option to import like the help file says....

I'll try fitting Arlet's core in together with some simple address decoding and the ROM. Maybe then it will give me more options!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

If it doesn't work with the ROM, I have a different method that I've used before. See this link for my ROM sources:

http://ladybug.xs4all.nl/arlet/fpga/source/rom_OS.v

The ROM is made from 2 parallel 4-bit wide block RAMs to create 8x4kB.
It includes the ROM contents using verilog `include statements. The included file uses 'defparam' statements to init the block RAM contents. You can see an example of what it looks like here:

http://ladybug.xs4all.nl/arlet/fpga/source/rom_F000L.v

I use a simple C program to convert a binary file into those 'defparam' lines.

Thanks for the offer!

But looking at the syntax for a .COE file, it looks pretty easy. I just need to find a hex editor that can output a text file with a comma delimiter. Then I can copy and paste, then rename the .txt to .coe...

HHD software has such a hex editor called NEO. I've actually had it installed for awhile now, even though I use HxD primarily. The 14 day trial has ended quite awhile ago, so I can't take advantage of this feature yet...

I'll try to reinstall a new version, with a new 14 day trial, on another computer to see if it is worth buying...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Instead of using an editor, you can also use a simple program or script to do the conversion.

A quick google search for "bin2coe" led to this C program:

http://www.sfc.wide.ad.jp/~macchan/wiki/index.php?plugin=attach&refer=FPGA%E9%96%8B%E7%99%BA%E7%94%A8%E3%83%A6%E3%83%BC%E3%83%86%E3%82%A3%E3%83%AA%E3%83%86%E3%82%A3&openfile=bin2coe.c

I haven't tried it, but it looks like it should do the trick.

Regrettably, I'm not familiar with the C language, but all suggestions welcome! A friend of mine at work who is used to writing scripts suggested a program called ultraedit. It's a text editor and was able to hunt for and replace characters. In this case hunt for a space, and replace with comma. It worked, but it costs $40....

This HHD piece of software is very nice though. I think I'm going to purchase it. I don't buy much in the way of software, and maybe I shouldn't. Maybe I'll try to install it on a machine with no battery for the BIOS with incorrect dates, etc. and see if it still installs. If it doesn't I'm going to have complaints...

Still, it does what I need a real hex editor to do. That is, as a hex editor, it should have a text editor under it's "belt', which it does. Seems to have much more also...

My last 2 days off from work have passed by very quickly! Sorta been stuck, but not for long! ........

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Are you using Windows or Linux ?