Since after the costs of the PCB's to be fabricated, the next highest costs is RAM I was wondering how much of a need would there be to make sure I don't "over volt" the RAM.

I've been looking at Cypress's CY7C1069AV33-10ZXC SRAM which is listed as a 3.0-3.6V due to the fact its a 2Mbyte part running at 10ns. If I fed it its own regulated VCC of 3.6V and I was running the 65C816 at 3.6V as well I'd be stuck to the 15Mhz range per WDC datasheet. However by feeding the RAM its own regulated VCC and using the 65C816 at ~4.25-4.5V I would be able to get the 65C816 up to the 16-18Mhz range.

But I wanted to know if the 65C816 would like being fed the lower output of the 3.6V RAM or would the RAM like the higher voltage of the ~4.25-4.5V 65C816?

Cause I am thinking data bus isolators that will allow the use of 5V on one side and the 3.6V on the other side would induce additional delays in the data which wouldn't be good either.

Dimitri

Certainly not! The FPGA on the Godil runs on 1.2V. Between the FPGA and 5 Volt outer world you find a 5V level shifters, SN74CB3T16211, capable of 100 MHz.

Edit: 100, not 10 MHz

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The Cypress chip is specced at typ. 3.3V and the datasheet says VCC +0.3V at the inputs is allowed - and they usually mean it!

If you are interfacing just with TTL levels it's no problem (and also mentioned in the datasheet). But most certainly you don't have TTL but CMOS level I/Os - so this is a no-go.

Usually manufacturers explicitly mention it in the datasheet if the I/Os are 5V tolerant (for example Xilinx XC95..XL series), so be careful with this.

If you want to interface 3.3V logic with 5V logic you need a level shifter. The CB3T series might be what you are looking after, they have a low propagation delay of 0.25 ns and are used, for example, in the "GODIL" modules:

http://focus.ti.com/docs/prod/folders/p ... 16211.html

so long,

Hias

I'd look at using 5 volt RAM and avoiding the complications of level shifters. Take a look at Cypress' CY7C1049D (stocked by Mouser and Digi-Key), which is a 512Kb * 8 async SRAM with a 10 ns access time and a straightforward bus interface. I used the smaller 128Kb * 8 version in my POC unit. You'll need four of these parts, of course, to get the same amount of storage as you would with the CY7C1069AV33 type, but you may decide that's less an issue than trying to work with the TSSOP or BGA packages in which level shifters are typically made, not to mention having to provide a 3.3 volt power source.

BTW, the cost of four of the Cypress CY7C104D is about the same as one of the CY7C1069AV33-10ZXC. The only real penalty is slightly more PCB real estate consumed and a bit more soldering.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Dimitri,

I would avoid the whole issue of voltage level translation. I was facing similar issues in my project... I was all about 5V ONLY and refused to even look at 3.3V parts.

However, if speed is your main concern, you will sooner or later face the fact that 5V parts are a dying breed. No problem inherently with 5V, although you will pay more for your parts, and I'm sure the distributor is happy to get rid of them as well!

I would recommend sooner than later you seriously start to consider 3.3V. Don't fixate on the '816 spec for VDD vs FREQ either. Consider that a conservative absolute minimum speed rating!

Just my 2 cents m8. Good luck!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Ruud,

Thank you for the information on the level shifters.

HiassofT,

Interesting to note the TTL verses CMOS differences.

BigDumbDinosaur,

I would look at 5V RAM but I want 4MBytes onboard, the 3.3V allows me to do it with 2 chips, I'd require 8 of them for the 5V chips.

ElEctric_EyE,

Yes I like 5V, as that is what I've always used. However I am inclined to use 3.3V as well execpt I am looking at that speed chart, and Garth had mentioned if your over the voltage that WDC specifies, then the processor would be alittle more tolorant on timing issues if I understood him correctly. Hence why going to the higher side of the voltage band in my mind would have been ideal.

I need to make sure everything is 60ns or under for the system to work at 16Mhz. As of now, using a PLD and the EPROM (OTP) for the BIOS ROM, I am right at 60ns assuming the PLD I end up using can do the full address decoding (whole 24-bit addressing instead of using any glue logic for that function if that is possible, I think it should be) in no more then 15ns. So I am right at the limit of the delays from the EPROM and the PLD.

Again I am assuming at best I'd get the worst case delays. Just because its better to work expecting the worst and smiling when you get the best, then hoping for the best and getting stressed due to problems you need to fix in the future.

Dimitri