Hi Ed,
I've been tinkering around a bit more with that board.
BigEd wrote:
Hi André
You mention "the same problem" but I'm not sure exactly what that is.
The problem is that the CPLD pulls the CPU data bus low at inappropriate times. The board is selected in a 16 byte address space, and one of the addresses is not served by the CPLD, but by a '245 buffer. So once that single address is selected, the CPLD pulls low the data bus.
(Edit: the version posted here only uses 3 addresses in the CPLD and has all the others but the one for the '245 unused - I checked that only this single address for the '245 is affected by setting this to Z and all others addresses to all-zeros and it's still working)
Quote:
Only external interface signals can be tristate, and they should be tristated with a simple expression. Your
Code:
data <= dataout when (dataout_en = '1') else (others => 'Z');
should be fine.
Then, there should be no other Z in your design. And yet you have this code, with a comment:
Code:
-- read any of the registers
ReadReg : process(phi2, muxInt, Nsel, dataRegister, rNw, regsel, byte, page, bank)
begin
case regsel is
[snip]
when others =>
-- this must be high-Z, all-zeros breaks (mangles data)
dataout <= "ZZZZZZZZ";
--dataout <= (others => '0');
end case;
end process ReadReg;
that all-zeros is broken, which is highly suspicious.
In the meantime I also tried all-ones, and this actually works out ok (similar to the Zs)! So it seems there is some kind of open-collector going on internally. This also justifies my "pulls the databus low" from above.
I tried some patterns in that dataout assignment, and only when a bit is set to zero here, the data bus is pulled low. one and Z are ok.
Quote:
Because you have internal Zs, I wouldn't be surprised to see this code synthesise poorly.
Yes, there is an extra set of cells used when the value is set to Z. But when I set the value to all-ones, I get the same lower number of cells used as with all-zeros, but it works.
Quote:
In this case you should be in don't-care territory - zeros or all ones should work equally well.
That's what I thought and that's why I am asking here, because my observations say otherwise. Might really be something wrong, or I am missing an important point, after all I'm new to CPLDs.
Quote:
So what does "mangles data" mean here - what did you see? If you put a specific bit pattern in for this case, when does it appear?
see above, thanks for the hint!
Quote:
In hardware terms, the first statement - the one-liner - is the tristate driver, and the big ReadReg process is the multiplexer which drives it - if you see the wrong data then you need to check that this mux is described correctly. (Actually it looks like nichtsnutz has already said all this...)
And here I need some help. How would I check that? I tried to generate a schematics in ISE Webpack, but did not see anything suspicious, but I am not sure if I can read that.
Many thanks for your help!
André