So as it has been suggested by a few of the experts here that I should try to do something a little more simple my first time out of the box here so I scaled back my board project. I dont have the serial IO setup yet but will be a sub board from the CPU. I have been thinking of using a 16550 uart for the serial, Although Its a weird chip to interface too.

so here is the memory map of this schematic
MAIN BOARD Memory Map
0-53247 $0-CFFF RAM
53249-57343 $D000-DFFF IO
57344-65535 $E000-FFFF 8K ROM
65536-2097151 $10000-1FFFFF RAM

Should be pretty self explanatory. might have some errors? Of course comments are encouraged.

In addition I have provided for your viewing pleasure the serial card so i can interface with this unit 16550 serial
I made serial 1 at D000 and serial 2 at D008 If I read the data sheet right....

should read:

57344-65535 $E000-FFFF 8K ROM

Lol, My bad.. got the decimal numbers right

I've had a quick look at your schematics. Some comments:

- The RAM /WE signal is an AND of R/W and Phi2. So your RAM will always(!) be written to except when the CPU reads during PHI2 high. The best way to create the /WE signal is to invert R/W, and NAND it with Phi2. So /WE only goes low when PHI2 is high, AND R/W is low - which is exactly a Phi2-qualified low-active write signal.

- You're using VDA (and VDA only!) to detect access to the ROM. This means the CPU cannot fetch instructions from the ROM - well, ok it can fetch the opcode byte (VDA=1, VPA=1), but not any operand (VDA=0,VPA=1). Also you cannot read any data table values or constants from the ROM (VDA=1, VPA=0). My best advice would be to ignore VDA/VPA for now. Instead you should use R/W here as well, to not try to write into the ROM chip.

- The memory map concerning the ROM is wrong. The ROM is selected in ANY of the 256 banks, not only in the first one - You only use Address bits A13-A15 and VDA - but not A16-A23 to produce the ROM's select line (on IC12)

- The RAM select logic is using VDA and VPA as enable signals, both must be 1 to enable RAM.That actually is only the opcode fetch. For operand fetch, VDA is 0, for data reads VPA is 0. As I said before, ignore VDA/VPA for now.
[Edit: VPA must be 0, VDA must be 1, but that is only data access - you can't put any programs in that RAM. Still: ignore VDA/VPA for now]

- The output of IC15 will never be low. You tie some of the many NAND inputs to zero, so the AND will never be 1, and the inverted output will be constant 1. Don't think that's what you intended.

That's what I found for now, hope it helps you with your design.

André

I took a real quick gander and noted that you left BE floating on the MPU. You should pull it up to Vcc with a 3.3K resistor. I'll look more closely at the circuit later on and comment.


I wouldn't use the 16550. To much board real estate and a strange programming mode. I used the NXP 2692A DUART in my POC unit and found it relatively easy to interface and program. Also, you get two serial ports for the price of one.


If I may make a suggestion, the schematic might be a little easier to follow if you use net symbols instead of running wires everywhere. Depending on the software you use, the use of nets may make it easier to detect errors and assist in PCB layout.


As i earlier suggested, take a look at the NXP 2692A (available as PDIP40 or PLCC44). It'll be less work to connect to the 65xx style bus. Also, look at the MAX238, which has sufficient transceivers for two EIA-232 channels. It's basically two MAX232s in one 24 pin package (DIP or SOT).

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

@GARTHWILSON, Cleaned it up a bit and will look at the NXP 2692A IC, the 16550's were just something I have in the parts bin, so I was thinking of using them based on immediate availability, Thanks

@fachat, I think I got it all better now. stripped the VPA/VDA out of the Rom circuit, inverted IC15, I only have 3 IC's deep on worst case so that would be at most 16ns prop delay.

Take a look at Version 7

Schematic

Why not? So far I always used this IC, starting with the 8250. Concerning the interface: take a 74F139 to create the RD and WR signal using ChipSelect, PHI2 and R/W as input.


Ehhh, being Dutch, what does this mean ???


Would you mind to explain this? I never had problems with programming these IC's; ML or Pascal.

I first used a 8250 with a Commodore 64 in a big paper factory to select some specific bytes out of a stream of data coming from scales weighting fresh made paper roles of about 1200 KG. They only noticed when somebody opened the box out of curiousity :)

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real estate = Immobilie (in German). I.e. it takes to much space on the board, after all it's a 40 pin chip. The 6551 could do the job in a 28 pin package (not even counting the support '139 you mentioned) The 6551 has other drawbacks though...

André

I didn't have problems with programming the 16540 as well. And what I really love is the FIFO buffer (which helps a lot with my - unfortunately high latency - multitasking operating system...)

But I'm open to looking into other solutions (as long as they have a FIFO...)

André

- you don't need IC13A as XOR, you can just use one of the AND gates you have left. And the AND even replaces IC6F. Write down a logic table to see how it works (hint: you don't need to handle both inputs being 0 at the same time)

- IC12B still combines VDA and VPA such that the output is 1 ONLY during opcode byte fetch. (BTW: that's an AND not a NOR as your description says). I.e. you access the RAM only for opcode fetch, nothing more.
And following that signal to the IC9 input you access I/O and ROM always - except for opcode byte fetches. And "opcode byte fetch" really means what it says: the single opcode byte. Because the operands have VDA=0. For example "LDA #$00" in memory is "A9 00" - A9 is fetched with VDA=1,VPA=1, while 00 is fetched with VPA=1, VDA=0. In your setup the A9 must be in RAM, while 00 must be in the ROM.

- your comments "PHI0 see note" and "PHI2 see note" are on two signals where PHI0 is the CPU's PHI2 input and PHI2 is the inverted of PHI1. That is against the common convention that PHI1 is the inverted of PHI0 and PHI2 has the same phase as PHI0.

- I don't know what tool you use to draw the schematics. Some of the dots that indicate that two crossing signals are connected are missing, some are in the wrong place. It is also much easer to read the schematics if you name all signals appropriately and, as in my schematics, I basically write the name of every signal on every pin connection on every IC. If I have long signal traces across the schematics, from time to time I even name every signal trace, just so I can follow it and be sure not to mix them up when reading.

- Again, the ROM is still accessed in each of the 256 64k banks, i.e. at $00E000-$00FFFF, $01E000-$01FFFF, $02E000-$02FFFF, ..., $FFE000-$FFFFFF. Not sure if you want that.

- Also, the RAM is mirrored too: Each RAM chip comes twice in your memory map (you don't use A19!), and the 4M memory selected by IC10 are mirrored 4 times (you don't use A22-A23!): As an example IC1 is from $000000-$07FFFF but also mirrored at $080000-$0FFFFF. Then IC1 is selected again at $400000-$47FFFF, $480000-$4FFFFF, $800000-$87FFFF, $880000-$7FFFFF, $C00000-$C7FFFF, $C80000-$CFFFFF. Not sure if you want that either.

- Currently your VDA/VPA logic avoids that RAM and ROM are addressed at the same time. You should rather take the low active ROM select and stick it into IC10 G1 to ensure that RAM is not selected when ROM is selected. You should also decide whether you want all the mirroring.

André

I will have to ponder this one for a minute. Make a logic table up like you say and see what goes where. Thanks for helping me out here.

For what its worth. .... Schematic v8

For what it's worth...

- Still IC15 will never give a an active (low) signal - you still pull some NAND inputs to ground

- IC16C now gives a correct low active "valid access" signal (i.e. the output is low when either VDA or VPA is high. Good. But you put it into IC10 G1 input (high active enable). So your RAM is only accessed on invalid cycles (VDA and VPA both 0).

Sorry, didn't look any further

André

Yea Im seeing it today. NAND was the wrong logic, I have quickly updated the schematic with NOR and a NAND to get low to the 154 enable



Schematic v9