Hallo allemaal,


I created a new 6502 core. It is part of my core for the Godil. I scrapped all the Godil parts except the 49 MHz clock. http://www.baltissen.org/zip/rb65-10.zip contains two VHDL's and a common test bench. The 'd' version creates a double clock out of PHI0 which enables me to execute some opcodes much faster then an original 6502. The 's' version uses the original clock.
A FPGA can be so fast that the data has gone from its data bus within seconds while some IC's require the data to be present for 10-20 ns. This is done by creating a shifted PHI0, PHI_i called, that is used to control the output of the data bus.

What are the biggest differences with the well known T65:
- a drawback: mine is almost twice as big.
- my VHDL can be read and understood by any person familiar with a 6502 but not with VHDL.
- every opcode is described
- I don't support illegal opcodes but once I know how they act, I can add them in an instance (try that in T65 !)
- I can replace KILL opcodes by my own ones with the same ease.

Questions and comment is welcome!

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Hi Ruud!

My congrats!

At what speed does it run, did you test it already? How did you test the correctness of the opcodes?

I'll sure have a look.

André

excellent! I'll take a look too. I still need to get a resynth of T65 to compare to retromaster's recent 6502 core as well.

I wonder if the fast clock-to-Q of the databus is the cause of some of the problems we had interfacing FPGA to existing systems.

Would you be happy to add a license to the files? (MIT-style if you really don't care much, or LGPL if you want to ensure the source stays open) As you may know, just declaring something to be in the public domain, or saying nothing, can get in the way of redistribution.

Cheers
Ed

Ruud, have you fitted your core into any particular device for a real world test?

As far as keeping it truly opensource, maybe check out the opencores.org site?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hallo allemaal,

Everything that can be downloaded from my site and is announced in public can be considered as freeware: http://www.baltissen.org/newhtm/copyrights.htm , third dot.

The VHDL has been tested in my Godil on my emulator. This emulator is 486SX-25 laptop on a dockingstation that holds an 96 I/O-lines ISA card. The laptop emulates a board with RAM and ROM and generates PHI0 at about 300 bytes/sec. Gideon Zweijtzer, the creator of the 1541Ultimate, www.1541ultimarte.net , hasn't seen anything why my VHDL shouldn't run at 1 MHz or higher. The only point of attention would be the timing of my "double clock" signal at higher frequencies.

The correctness is tested using a self written ROM. My question regarding the behaviour of PHP was the result of this test: my VHDL completed the test while Gideon's VHDL created an error. I only have to hope that so far my test program covers all possible issues. And to be honnest, it just occurs to me that I haven't tested IRQ and NMI :( But as I have no problems with BRK, I expect no problems with them as well.

I only just checked the timing: my VHDL completed the test in 7001 uS, Gideon's VHDL in 7010 uS and T65 in 7013 uS. So it seems I'm a bit too fast. Which is a bit funny because I had to extend quite some opcodes with a dummy cycle to stay cycle exact.

My future plans:
- replacing the 6502 of my VIC-20 with the Godil
- replacing the 6510 of my C64 with the Godil
- replacing the 8088 of an old IBM XT with the Godil :) Still using the 6502 core of course !!!
In case of the IBM I first program a fixed MMU that maps 8 KB of ROM, 4 KB of Video memory, 1 KB of I/O and RAM some where into the 64 KB range of the 6502. Next step is to add an extra address register plus opcodes similar/equal to the 65816.

Interesting for the C64 and C128 owners: parallel to the above I want to use the results of creating a 65816 to turn the Ultimate into a SuperCPU. I'm also thinhing about turning the Ultimate into a CP/M module. In the first place just a stand-alone, but faster Z80, like the original C64 module. But later I want to turn it into a complete computer where the C64/128 only acts as a terminal. Just like the Acorn BBC and the Z80 Second Processor.

Nice ideas, but not having won the Jackpot yet, lack of time prevents me to give you a time table.

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FPGAs really don't like bidirectional signals. For something designed as an FPGA soft core, you really should use separate D_in and D_out busses, and adopt a synchronous memory bus (synchronous busses scale to much higher speeds)

If the processor is part of a bigger desig, for example the 1541Ultimate, yes. But as said, this VHDL is an excerpt from the VHDL for my Godil. And here one must use this structure or the Godil cannot replace an existing CPU (or other IC). See http://www.OHO-Elektronik.de for more details.

EDIT: I just found out that I forgot to implement the RDY signal in my VHDL. But don't worry, I'll update it soon enough.

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Hi Ruud
thanks for clarifying the license (and for making your work available)

Please would you release your ROM? I'd be interested to run it on the visual6502. (Pehaps also on retromaster's)

Cheers
Ed

Oops, I thought it was included. I updated the ZIP: http://www.baltissen.org/zip/rb65-10.zip. Included are the ASM, BIN and LST as well. But this ROM isn't the original one; I "improved" it by adding other tests. And this afternoon I ran into a problem regarding the decimal flag at the end of the ROM, so be aware of this part.

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Thats great! Thank you very much. (There's always a problem with decimal mode!)

Hi Ruud
Have you withdrawn your zip archive? Or only renamed it? I wanted to have another look at your 8k self-testing ROM code.

Cheers
Ed

Hmmm. must have removed it by accident, sorry. OK, it has been put back: http://www.baltissen.org/zip/rb65-10.zip
As an extra:http://www.baltissen.org/zip/rb65-11.zip. This one contains a newer ASM, VHDL and the start of the VHDL for the 65816.

Have fun!

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Thanks! (Judging by line-count, the '816 will turn out to be something like twice as complex as the 6502. But a better metric will be when you have an implementation report from a working version - look forward to that day!)

It will. But OTOH the 816 core gave me an idea to simplify the 6502 core. Have a look at the following code:

I decided to combine both codes:

OK, very simplistic but I think you get the picture: the same code is reused for other instructions. It is effective because after two smaller concatenations (?) I reduced the load of the FPGA with 1 %.

An other idea is to drop the CASE statement and to use someting like "if (Opcode(3 downto 0) = "0001") then ...".

To be continued....

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I found out that combining instructions saved me about 20% of FPGA resources. The "if Opcode...." trick saved another 4% and I'm not finished yet. http://www.baltissen.org/files/RB65.vhd is the latest raw result. Checking the link I found out that the comment for the first block of instructions is missing: it are the various ASL, ROL, LSR, ROR, INC etc. instructions.

Again, to be continued....

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